参数资料
型号: APT7843
厂商: Anpec Electronics Corporation
英文描述: Touch Screen Controller
中文描述: 触摸屏控制器
文件页数: 2/18页
文件大小: 622K
代理商: APT7843
Copyright ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
APT7843
www.anpec.com.tw
10
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
6-4
A2-A0
Channel Select Bits. Along with the SER/DFR bit,
these bits control the setting of the multiplexer
input, switches, and reference inputs, as detailed in
Tables I and II.
MODE
12-Bit/8-Bit Conversion Select Bit. This bit controls
the number of bits for the following conversion: 12-
bits(LOW) or 8-bits(HIGH).
2
SER/DFR Single-Ended/Differential Reference Select Bit.
Along with bits A2-A0, this bit controls the setting of
the multiplexer input, switches, and reference
inputs, as detailed in Tables I and II.
1-0
PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE III. Order of the Control Bits in the Control
Byte.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
SA2
A1
A0
MODE SER/DFR
PD1
PD0
TABLE V. Power-Down Selection.
PD1 PD0
PENIRQ DESCRIPTION
0
Enabled Power-down between conversions. When
each conversion is finished, the converter
enters a low power mode.
0
1
Enabled Reserved for future use
1
0
Enabled Reserved for future use.
1
Disabled No power-down between conversions,
device is always powered.
DCLK
CS
DOUT
BUSY
DIN
tACQ
ldle
Acquire
Conversion
ldle
(MSB)
(LSB)
11 10 9
8 7 6
5 4
3 2
1 0
(START)
S A2 A1 A0
PD1 PD0
SER/
DFR
MODE
18
8
1
FIGURE 5. Conversion Timing, 24-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required
with Dedicated Serial Port.
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