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| 型号： | APW7057KC-TU |
| 厂商： | Anpec Electronics Corporation |
| 英文描述： | High Power Step-Down Synchronous DC/DC Controller |
| 中文描述： | 高功率降压型同步DC / DC控制器 |
| 文件页数： | 10/14页 |
| 文件大小： | 154K |
| 代理商： | APW7057KC-TU |
Copyright
ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
APW 7057
www.anpec.com.tw
10
Application I nformation
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition
loss.The switching internal, t
sw
, is a function of the
reverse transfer capacitance C
RSS
. Figure 3 illustrates
the switching waveform internal of the MOSFET.
The (1+TC) term is to factor in the temperature depen-
dency of the R
DS(ON)
and can be extracted from the
“R
DS(ON)
vs Temperature” curve of the power MOSFET.
Layout Considerations
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 4 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
Decoupling capacitor C
IN
provides the bulk capaci
tance and needs to be placed close to the IC since
it will provide the MOSFET drivers transient current
requirement.
The ground return of C
IN
must return to the combine
C
OUT
(-) terminal.
Capacitor C
BOOT
should be connected as close to
the BOOT and PHASE pins as possible.
V
IN
V
OUT
Q1
L1
4
8
2
U
1
1
5
C
OUT
C
IN
Figure 4. Recommended Layout Diagram
+
+
APW7057
UGATE
LGATE
VCC
PHASE
BOOT
C
HF
Q2
d
Time
V
DS
tsw
Figure 3. Switching waveform across MOSFET
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