参数资料
型号: APX803-23SAG-7
厂商: Diodes Inc
文件页数: 5/10页
文件大小: 0K
描述: IC MPU RESET CIRC 2.25V SOT23-3
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.25V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: TO-236-3,SC-59,SOT-23-3
供应商设备封装: SOT-23-3
包装: 标准包装
其它名称: APX803-23SAG-7DIDKR
APX803
3-PIN MICROPROCESSOR RESET CIRCUIT
Functional Description
Microprocessors (μPs) and microcontrollers (μC) have a reset
input to ensure that it starts up in a known state. The APX803
drive the μP’s reset input to prevent code-execution errors during
power-up, power-down, or brownout conditions. They assert a
reset signal whenever the V CC supply voltage declines below a
preset threshold, keeping it asserted for at least 140ms after V CC
has risen above the reset threshold. The APX803 has an
open-drain output stage.
Ensuring a Valid Reset Output
Down to V CC = 0
RESET is guaranteed to be a logic low for V CC > 1V. Once V CC
drift to undetermined voltages.
This presents no problem in most applications since most μP and
other circuitry is inoperative with V CC below 1V.
Interfacing to μP with Bidirectional Reset Pins
Since the RESET output on the APX803 is open drain, this
device interfaces easily with μ P/μC that have bidirectional reset
pins, such as the Motorola 68HC11.
Connecting the μ P supervisor’s RESET output directly to the
microcontroller’s ( μ C’s) RESET pin with a single pull-up resistor
allows either device to assert reset.
Supervising and monitoring Multiple Supplies
exceeds the reset threshold, an internal timer keeps
RESET
Generally, the pull-up resistor connected to the APX803 will
low for the reset timeout period; after this interval, RESET
goes high. If a brownout condition occurs (V CC dips below the
RESET reset threshold), RESET goes low. Any time
V CC goes below the reset threshold, the internal timer resets to
connect to the supply voltage that is being monitored at the IC’s
V CC pin. However, some systems may use the APX803
open-drain output to level-shift from the monitored supply to reset
the μP powered by a different supply voltage or monitor multiple
supplies that will be fed into 1 μC/μP reset input.
zero, and
RESET goes low. The internal timer starts after
V CC returns above the reset threshold, and
low for the reset timeout period.
RESET remains
When V CC falls below 1V, the APX803
RESET output no
longer sinks current — it becomes an open circuit. Therefore,
high-impedance CMOS logic inputs connected to RESET can
Block Diagram
RESET
V REF
Delay Circuit
Driver
/ RESET
APX803 Rev. 1
Document number: DS32132 Rev. 1 – 2
5 of 10
MARCH 2010
? Diodes Incorporated
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