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参数资料
| 型号： | ARA2000S23TR |
| 厂商： | ANADIGICS INC |
| 元件分类： | 放大器 |
| 英文描述： | RF/MICROWAVE NARROW BAND HIGH POWER AMPLIFIER |
| 封装： | SSOP-28 |
| 文件页数： | 4/20页 |
| 文件大小： | 254K |
| 代理商： | ARA2000S23TR |
12
Data Sheet - Rev 2.1
07-2001
ARA2000
DATA
CLOCK
ENABLE
OR
D
15: MSB
D
14
D
8
D
7
D
1
D
0: LSB
Table 6: Programming Word
LOGIC PROGRAMMING
Table 7: Data Description
Figure 17: Serial Data Input Timing
E
U
L
A
V
N
O
I
T
C
N
U
F
)
s
a
p
y
b
=
0
,
n
o
=
1
(
7
PA
/
N
6
PA
/
N
5
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
2
3
4
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
6
1
3
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
8
2
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
4
1
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
2
0
Pti
B
r
o
t
a
u
n
e
tt
A
B
d
1
Table 8: Device Address
O
T
U
P
N
I
L
E
V
E
L
C
I
G
O
L
E
C
I
V
E
D
S
E
R
D
A
1
C
0
C
)
1
C
(
6
1
n
i
P
)
0
C
(
5
1
n
i
P
00
0
10
1
0
01
0
1
11
1
T
I
B
A
T
A
D
5
1
D
4
1
D
3
1
D
2
1
D
1
D
0
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
e
u
l
a
V
7
P6
P5
P4
P3
P2
P1
P0
0
1
C0
C1
1
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ARA2001 | 制造商:ANADIGICS 制造商全称:ANADIGICS, Inc 功能描述:CATV Reverse Amplifier with step Attenuator |
| ARA2001S23 | 制造商:ANADIGICS 制造商全称:ANADIGICS, Inc 功能描述:CATV Reverse Amplifier with step Attenuator |
| ARA2001S23P0 | 制造商:Rochester Electronics LLC 功能描述: 制造商:ANADIGICS Inc 功能描述: |
| ARA2001S23TR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Miscellaneous |
| ARA2004 | 制造商:ANADIGICS 制造商全称:ANADIGICS, Inc 功能描述:Reverse Amplifier with Step Attenuator |
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