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| 型号： | AS1324-BTTT-12 |
| 厂商： | ams |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 1.2V TSOT23-5 |
| 设计资源： | Design Support Tool |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 1.2V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.5MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 包装： | 标准包装 |
| 供应商设备封装： | TSOT-23-5 |
| 其它名称： | AS1324-BTTT-12DKR |
AS1324
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9.6 Efficiency
The efficiency of a switching regulator is equivalent to:
Efficiency = (P OUT /P IN )100%
(EQ 8)
For optimum design, an analysis of the AS1324 is needed to determine efficiency limitations and to determine design changes for improved
efficiency. Efficiency can be expressed as:
Efficiency = 100% – (L 1 + L 2 + L 3 + ...)
Where:
L 1 , L 2 , L 3 , etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce losses, those four main sources should be considered for efficiency calculation:
(EQ 9)
9.6.1
Input Voltage Quiescent Current Losses
The V IN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. V IN current
results in a small (<0.1%) loss that increases with V IN , even at no load. The V IN quiescent current loss dominates the efficiency loss at very low
load currents.
9.6.2
I2R Losses
Most of the efficiency loss at medium to high load currents are attributed to I2R loss, and are calculated from the resistances of the internal
switches (R SW) and the external inductor (R L ). In continuous mode, the average output current flowing through inductor L is split between the
internal switches. Therefore, the series resistance looking into the SW pin is a function of both NMOS & PMOS R DS(ON) as well as the duty
cycle (DC) and can be calculated as follows:
R SW = (R DS(ON)PMOS )(DC) + (R DS(ON)NMOS )(1 – DC)
(EQ 10)
The R DS(ON) for both MOSFETs can be obtained from the Electrical Characteristics on page 4 . Thus, to obtain I2R losses calculate as follows:
I2R losses = I OUT 2(R SW + R L )
(EQ 11)
9.6.3
Switching Losses
The switching current is the sum of the control currents and the MOSFET driver. The MOSFET driver current results from switching the gate
capacitance of the power MOSFETs. If a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from V IN to
ground. The resulting dQ/dt is a current out of V IN that is typically much larger than the DC bias current. In continuous mode:
I GC = f(Q PMOS + Q NMOS )
Where: Q PMOS and Q NMOS are the gate charges of the internal MOSFET switches.
The losses of the gate charges are proportional to V IN and thus their effects will be more visible at higher supply voltages.
(EQ 12)
9.6.4
Other Losses
Basic losses in the design of a system should also be considered. Internal battery resistances and copper trace can account for additional
efficiency degradations in battery operated systems. By making sure that C IN has adequate charge storage and very low ESR at the given
switching frequency, the internal battery and fuse resistance losses can be minimized. C IN and C OUT ESR dissipative losses and inductor core
losses generally account for less than 2% total additional loss.
9.7 Thermal Shutdown
Due to its high-efficiency design, the AS1324 will not dissipate much heat in most applications. However, in applications where the AS1324 is
running at high ambient temperature, uses a low supply voltage, and runs with high duty cycles (such as in dropout) the heat dissipated may
exceed the maximum junction temperature of the device.
As soon as the junction temperature reaches approximately 150oC the AS1324 goes in thermal shutdown. In this mode the internal PMOS &
NMOS switch are turned off. The device will power up again, as soon as the temperature falls below +145°C again.
9.8 Checking Transient Response
The main loop response can be evaluated by examining the load transient response. Switching regulators normally take several cycles to
respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equivalent to:
V DROP = ? I OUT x ESR
(EQ 13)
Where:
ESR is the effective series resistance of C OUT .
? I OUT also begins to charge or discharge C OUT , which generates a feedback error signal. The regulator loop then acts to return V OUT to its
steady-state value. During this recovery time V OUT can be monitored for overshoot or ringing that would indicate a stability problem.
www.ams.com/DC-DC_Step-Up/AS1324
Revision 1.06
14 - 21
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