参数资料
型号: AS1324-BTTT-12
厂商: ams
文件页数: 9/21页
文件大小: 0K
描述: IC REG BUCK SYNC 1.2V TSOT23-5
设计资源: Design Support Tool
标准包装: 1
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.2V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.5MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
包装: 标准包装
供应商设备封装: TSOT-23-5
其它名称: AS1324-BTTT-12DKR
AS1324
Datasheet - D e t a i l e d D e s c r i p t i o n
8.1 Main Control Loop
During PWM operation the converters use a 1.5MHz fixed-frequency, current-mode control scheme. Basis of the current-mode PWM controller is
an open-loop, multiple input comparator that compares the error-amp voltage feedback signal against the sum of the amplified current-sense
signal and the slope-compensation ramp. At the beginning of each clock cycle, the internal high-side PMOS turns on until the PWM comparator
trips. During this time the current in the inductor ramps up, sourcing current to the output and storing energy in the inductor’s magnetic field.
When the PMOS turns off, the internal low-side NMOS turns on. Now the inductor releases the stored energy while the current ramps down, still
providing current to the output. The output capacitor stores charge when the inductor current exceeds the load and discharges when the inductor
current is lower than the load. Under overload conditions, when the inductor current exceeds the current limit, the high-side PMOS is turned off
and the low-side NMOS remains on until the next clock cycle.
When the PMOS is off, the NMOS is turned on until the inductor current starts to reverse (as indicated by the current reversal comparator
(IRCMP)), or the next clock cycle begins. The IRCMP detects the zero crossing.
The peak inductor current (I PK ) is controlled by the error amplifier. When I OUT increases, V FB decreases slightly relative to the internal 0.6V
reference, causing the error amplifier ’s output voltage to increase until the average inductor current matches the new load current.
The over-voltage detection comparator (OVDET) guards against transient overshoots by turning the main switch off and keeping it off until the
transient is removed.
8.2 Powersave Operation
The AS1324 uses an automatic powersave mode where the peak inductor current (I PK ) is set to approximately 200mA while independent of the
output load. In powersave mode, load current is supplied solely from the output capacitor. As the output voltage drops, the error amplifier output
rises above the powersave threshold signaling to switch into PWM fixed frequency mode and turn the PMOS on. This process repeats at a rate
determined by the load demand.
Each burst event can last from a few cycles at light loads to almost continuous cycling (with short sleep intervals) at moderate loads. In between
bursts, the power MOSFETs are turned off, as is any unneeded circuitry, reducing quiescent current to 30μA.
8.3 Short-Circuit Protection
In cases where the AS1324 output is shorted to ground, the oscillator frequency (f OSC ) is reduced to 1/13 the nominal frequency ( ? 115kHz).
This frequency reduction ensures that the inductor current has more time to decay, thus preventing runaway conditions. f OSC will progressively
increase to 1.5MHz when V FB /V OUT > 0V.
8.4 Shutdown
Connecting EN to GND or logic low places the AS1324 in shutdown mode and reduces the supply current to 0.1μA. In shutdown the control
circuitry and the internal NMOS and PMOS turn off and SW becomes high impedance disconnecting the input from the output. The output
capacitance and load current determine the voltage decay rate. For normal operation connect EN to V IN or logic high.
Note: Pin EN should not be left floating.
www.ams.com/DC-DC_Step-Up/AS1324
Revision 1.06
9 - 21
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