参数资料
型号: AS1335-BTDT-100
厂商: ams
文件页数: 3/19页
文件大小: 0K
描述: IC REG BUCK SYNC 1V 1.5A 10WFDFN
标准包装: 1,000
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1V
输入电压: 2.6 V ~ 5.25 V
PWM 型: 电压模式
频率 - 开关: 1.5MHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-TDFN(3x3)
AS1335
Datasheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
VIN 1
NC 2
10 SW
9 PGND
Pin Descriptions
Table 1. Pin Descriptions
EN 3
POK 4
GND 5
AS1335
11
8 GND
7 FB
6 RSI
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
Pin Name
VIN
NC
EN
POK
GND
RSI
FB
GND
PGND
SW
Description
Positive Supply Voltage . This pin must be closely decoupled to PGND with a ≥ 22μF
ceramic capacitor.
Not Connected.
Enable Input . Driving this pin above 1.4V enables the device. Driving this pin below 0.3V
puts the device in shutdown mode. In shutdown mode all functions are disabled, drawing
≤ 1μA supply current.
Note: This pin should not be left floating.
Power-OK Output. Open-drain output with 215ms delay. Connect a 100k Ω pull-up resistor
to V OUT or pin VIN for logic levels. Leave this pin unconnected if the Power-OK feature is
not used.
LOW Signal: Out of regulation
HIGH signal: Within Regulation (after 215ms delay)
Analog Ground.
Reset Input for POK. This input resets the 215ms timer of the POK signal.
As long as RSI is low the POK signal will work as described above.
A high input to RSI will reset the 215ms POK timer and delay the signal as long as RSI
stays high. A RSI low-to-high transition restarts the 215ms counter as long as the output
voltage is within regulation.
Note: Do not leave this pin floating.
Feedback Pin . Feedback input to the gm error amplifier. Connect a resistor divider tap to
this pin. The output can be adjusted from 0.6V to 5.25V by V OUT = 0.6V[1+(R1/R2)].
If the fixed output voltage version is used, connect this pin to V OUT .
Analog Ground. GND and PGND should only have one point connection.
Power-Ground. Connect all power grounds to this pin.
Switch Node Connection to Inductor. This pin connects to the drains of the internal main
and synchronous power MOSFET switches.
Exposed Pad. The exposed pad must be connected to PGND. Ensure a good connection
to the PCB to achieve optimal thermal performance.
Revision 1.03
2 - 18
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