参数资料
型号: AS1340A-BTDT-10-1K
厂商: ams
文件页数: 9/17页
文件大小: 0K
描述: IC REG BOOST SYNC ADJ 1.4A 8TDFN
设计资源: Design Support Tool
标准包装: 1
类型: 升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 2.7 V ~ 50 V
输入电压: 2.7 V ~ 50 V
频率 - 开关: 1MHz
电流 - 输出: 1.4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 8-TDFN(3x3)
其它名称: AS1340A-BTDT-10-1KDKR
AS1340
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1340 features a current limiting circuitry, a fixed-frequency PWM architecture, power-OK circuitry, thermal protection, and an automatic
powersave mode in a tiny package, and maintains high efficiency at light loads.
Figure 27. AS1340 - Block Diagram with Shutdown Disconnect Switch
L 1
3
SWVIN
6
SWOUT
4.7μH
4
POK
5
LX
V IN = 2.7V
to 5.5V
2
1.13V
C IN
1μF
VCC
PWM
Control
Sync Drive
Control
0.9 ?
V OUT
Good
+
V IN to 50V
1 MHz
Spread
Spectrum
Ramp Gen-
Slope
Compensator
?
Current
Sense
C FF *
R 1
1
EN
erator
Shutdown
Control
+
PWM –
Comp
Shutdown
R C
C P2
V C
AS1340
g m Error
Amp
+
8
FB
C OUT
Powersave
Powersave
Operation
Control
C C
1.25V
Ref
R 2
7,9 GND
* Optional
Automatic powersave mode regulates the output and also reduces average current flow into the device, resulting in high efficiency at light loads.
When the output increases sufficiently, the powersave comparator output remains high, resulting in continuous operation.
For each oscillator cycle, the power switch is enabled. A voltage proportional to switch current is added to a stabilizing ramp and the resulting
sum is delivered to the positive terminal of the PWM comparator.
The error amplifier compares the voltage at FB with the internal 1.25V reference and generates an error signal (V C ). When V C is below the
powersave mode threshold voltage the automatic powersave-mode is activated and the hysteretic comparator disables the power circuitry, with
only the low-power circuitry still active (total current consumption is minimized).
When a load is applied, V FB decreases; V C increases and enables the power circuitry and the device starts switching. In light loads, the output
voltage (and the voltage at FB) will increase until the powersave comparator disables the power circuitry, causing the output voltage to decrease
again. This cycle is repeated resulting in low-frequency ripple at the output.
The POK output indicates whether the output voltage is within 90% of the nominal output voltage level or not. When EN is low, the circuit is not
active and POK gives a high signal when connected to V CC by a pull-up resistor. When EN goes high, POK goes low after approximately 50μs
and will go high when the output reaches 90% of the nominal output voltage (see Figure 20 on page 7) . When input and output voltage are
almost the same, it may happen that the POK Signal does not go low because V OUT reaches 90% before the delay has expired. The open-drain
POK output sinks current, when EN is high and the output voltage is below 90% of the nominal output voltage.
Thermal protection circuitry shuts down the device when its temperature reaches 145oC.
www.ams.com/DC-DC_Step-Up/AS1340
Revision 1.20
9 - 17
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