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参数资料
| 型号： | AS3510-T |
| 厂商： | ams |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC CODEC AFE ANALOG 49-CABGA |
| 标准包装： | 2,250 |
| 类型： | 音频编解码器 |
| 应用： | 便携式音频，电话 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 49-WFBGA |
| 供应商设备封装： | 49-CSBGA（7x7） |
| 包装： | 带卷 (TR) |
Product Brief AS3510
Rev. 1v2, June 2004
CONFIDENTIAL
Page 4 of 19
Inputs
Output
ADC-Modes
ENADC
I2S-Clocks
LRCK, SCLK,MCLK
MICP/MICN
SDO
OFF
L
X
static L
ADC_ON
H
LRCK up to 50kHz
MCLK … 128*F(LRCK)
SCLK … >=34*F(LRCK)
Differential analog
input
to be converted to
digital output
SDI serial data output
Ieft justified to LRCK with
MSB first at 2nd SCLK
edge
Table 3
ADC Operating Modes
Nodes:
-
There are 16bit presented at SDO at each cycle but just the first 14 do have relevalt data.
-
The ADC is a single channel (mono) path. The same SDO bitstream is presented for left and right channel of one cycle.
-
The ADC sampling rate is equal to LRCK/4. This means that the SDO bitstream gets updated at each 4th cycle of LRCK.
-
SCLK has to have at least 34 cycles within one LRCK cycle
2*(16bit data + the leading empty bit)
ams
AG
Technical
content
still
valid
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