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| 型号： | AS3510-T |
| 厂商： | ams |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC CODEC AFE ANALOG 49-CABGA |
| 标准包装： | 2,250 |
| 类型： | 音频编解码器 |
| 应用： | 便携式音频，电话 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 49-WFBGA |
| 供应商设备封装： | 49-CSBGA（7x7） |
| 包装： | 带卷 (TR) |
Product Brief AS3510
Rev. 1v2, June 2004
CONFIDENTIAL
Page 5 of 19
Functional Description
Audio DAC
Block Description
This block is the complete audio DAC delivering 93dB
dynamic range. It is comprised of a multibit sigma-delta
modulator with dither option and a switched-capacitor
analog filter. This architecture provides a high insensitivity
to clock jitter. A digital interpolation filter increases the
sample rate by a factor of 8 using 3 linear phase, half-band
filters cascaded, followed by a first order SINC interpolator
with a factor of 8. This filter eliminates the images of
baseband audio remaining only the image at 64* the input
sample rate. Optionally, a dither signal can be added that
may reduce eventual noise tones at the output. However,
the use of a multibit delta-sigma modulator already
provides extremely low noise tone energy.
Signal Description
Setting DACPD to 1 forces the analog section to power-
down. For Normal-Operation the I2S signals have to be
applied as shown below:
15
0
17
2
0
1
15
0
17
2
0
1
MCLK
LRCK
SCLK
SDATA(16)
SDATA(18)
64 MCLK cycles
Left Channel
64 MCLK cycles
Right Channel
Figure 2
I2S Waveforms
The LRCK defines if the transferred data is for the left or
right channel (L=left).
With the rising edge of the serial clock SCLK, the
inputdata gets strobed.
The data word at SDATA is max. 18 bit with MSB first and
2nd complement coded. All I2S signals change state with
falling edge of SCLK.
code
hex value
Max. positive code
1FFFF (hex)
+1
00001 (hex)
0
00000 (hex)
-1
3FFFF (hex)
Max. negative code:
20000 (hex)
Table 4
I2S Code Values
If the dataword length is less than 18 bit, zeros have to be
added to avoid any offset value.
The frequency of master clock MCLK has to be 128 times
the input sample rate (F(LRCK)*128) with low jitter. The
rising edge of MCLK should be separated by >10ns from
LRCK edges.
There are 2 pins needed for the generation and decoupling
of reference-voltages for the DAC. AGND is AVDD/2 and
VREF is equal to AVDD. Both pins have high output
resistance which provides a suitable lowpass filter for
these reference voltages with external capacitors of 10uF
in parallel with 100nF.
The supply lines are separate for digital DVSS / DVDD and
analog AVSS / AVDD to minimise coupling influences.
The analog output is differential stereo signal at nodes
OUTRN, OUTRP and OUTLN, OUTLP respectively.
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