参数资料
型号: AS3607A-BQFP
厂商: ams
文件页数: 40/71页
文件大小: 0K
描述: IC PMU PROGR STARTUP 36-QFN
标准包装: 20,000
应用: 手持/移动设备
电流 - 电源: 160µA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-VFQFN 裸露焊盘
供应商设备封装: 36-QFN(6x6)
包装: 带卷 (TR)
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 21. CVDD3 Register
Name
CVDD3
Base
2-wire serial
CVDD3 DC/DC Buck Regulator Control Register
Default
00h
Offset: 17h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7
Bit Name
CVDD3_fast
Default
0
Access
R/W
Bit Description
Selects a faster regulation mode for CVDD3 suitable for larger load changes.
0: normal mode, Cext=10uF
1: fast mode, Cext=22uF required
6:0
VSEL_CVDD3<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Table 22. Hibernation Register
Name
Hibernation
Base
2-wire serial
PMU Hibernation Control Register
Default
00h
Offset: 17h-4
Hibernation starts when writing this register, except hibernation via GPIO is selected.
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input. This register MUST NOT be read back!!!
Bit
7
6
Bit Name
-
KEEP_PVDD4
Default
0
0
Access
n/a
W
Bit Description
Keeps the programmed PVDD4 level during hibernation.
0: power down PVDD4
1: keep PVDD4
5
KEEP_PVDD3
0
W
Keeps the programmed PVDD3 level during hibernation.
0: power down PVDD3
1: keep PVDD3
4
KEEP_PVDD2
0
W
Keeps the programmed PVDD2 level during hibernation.
0: power down PVDD2
1: keep PVDD2
3
KEEP_PVDD1
0
W
Keeps the programmed PVDD1 level during hibernation.
0: power down PVDD1
1: keep PVDD1
2
KEEP_CVDD3
0
W
Keeps the programmed CVDD3 level during hibernation.
0: power down CVDD3
1: keep CVDD3
1
KEEP_CVDD2
0
W
Keeps the programmed CVDD2 level during hibernation.
0: power down CVDD2
1: keep CVDD2
0
KEEP_CVDD1
0
W
Keeps the programmed CVDD1 level during hibernation.
0: power down CVDD1
1: keep CVDD1
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