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| 型号： | AS3648-ZWLT |
| 厂商： | ams |
| 文件页数： | 7/39页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR 2000MA FLASH 13WLCSP |
| 标准包装： | 10,000 |
| 恒定电压： | 是 |
| 拓扑： | PWM，升压（升压） |
| 输出数： | 2 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 闪灯/白光 |
| 频率： | 4MHz |
| 电源电压： | 2.7 V ~ 4.4 V |
| 输出电压： | 2.8 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 13-UFBGA，WLCSP |
| 供应商设备封装： | 13-WLCSP（2.25x1.5） |
| 包装： | 带卷 (TR) |
| 工作温度： | -30°C ~ 85°C |
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AS3648
Datasheet, Confidential - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I C mode timings - see Figure 3 on page 7
2
f SCLK
SCL Clock Frequency
1/
t TIMEO
400
kHz
UT
START Condition
t BUF
t HD:STA
t LOW
t HIGH
t SU:STA
Bus Free Time
Between a STOP and
START Condition
Hold Time (Repeated)
7
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
1.3
0.6
1.3
0.6
0.6
μs
μs
μs
μs
μs
Data Hold Time
Data Setup Time
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
C B
C I/O
8
9
Rise Time of Both
SDA and SCL Signals
Fall Time of Both SDA
and SCL Signals
Setup Time for STOP
Condition
Capacitive Load for
Each Bus Line
I/O Capacitance
(SDA, SCL)
C B — total capacitance of one bus line in pF
0
100
20 +
0.1C B
20 +
0.1C B
0.6
0.9
300
300
400
10
μs
ns
ns
ns
μs
pF
pF
1. For VBAT=4.5V, SCL=1.8V, SDA=1.8V maximum I STANBY is <16μA.
2. To improve efficiency at low output currents, the active part of the internal switching transistor PMOS is reduced
in size to 1/5 its original size. This reduces the current required to drive the PMOS transistor and therefore
improves overall efficiency at low output currents.
3. The maximum current driving capability depends on supply voltageV VIN , LED forward voltage and coil peak cur-
rent limit.
4. Due to slope compensation of the current limit, I LIMIT changes with duty cycle - see Figure 16 on page 10 .
5. The logic input levels V IH and V IL allow for 1.2V or 1.8V supplied driving circuit
6. A pulldown current of 36μA is equal to a pulldown resistor of 42k ? at 1.5V
7. After this period, the first clock pulse is generated.
8. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IHMIN of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
9. A fast-mode device can be used in a standard-mode system, but the requirement t SU:DAT = to 250ns must then
be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t R max +
t SU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
www.austriamicrosystems.com/AS3648
1.5-4
6 - 38
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS3648-ZWLT-500 | 功能描述:IC WHITE LED FLASH DVR 13WLCSP RoHS:是 类别:集成电路 (IC) >> PMIC - LED 驱动器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 恒定电流:- 恒定电压:- 拓扑:升压（升压），切换式电容器（充电泵） 输出数:1 内部驱动器:是 类型 - 主要:背光 类型 - 次要:白色 LED 频率:625kHz ~ 875kHz 电源电压:2.7 V ~ 5.3 V 输出电压:5V 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽） 供应商设备封装:10-µMAX 包装:带卷 (TR) 工作温度:-40°C ~ 85°C |
| AS36490FLF | 制造商:TT Electronics / IRC 功能描述:AS36490FLF |
| AS36490HLF | 制造商:TT Electronics / IRC 功能描述:AS36490HLF |
| AS36490JLF | 制造商:TT Electronics / IRC 功能描述:AS36490JLF |
| AS36491FLF | 制造商:TT Electronics / IRC 功能描述:AS36491FLF |
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