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参数资料
| 型号： | AS5040-ASST |
| 厂商： | ams |
| 文件页数： | 26/34页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER PROG 10-BIT 16-SSOP |
| 应用说明： | AS5000 Series Magnet Selection Guide AS5000 Series Magnets for Extended Vertical Range |
| 标准包装： | 1 |
| 传感范围： | 45mT ~ 75mT |
| 类型： | 线性，旋转编码器 - 可编程 |
| 电源电压： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 电流 - 电源： | 21mA |
| 电流 - 输出（最大）： | 4mA |
| 输出类型： | 正交，带刻度角（增量） |
| 特点： | 可编程 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 804 (CN2011-ZH PDF) |
| 配用： | AS5040 PB-ND - BOARD PROGRAM AS5040 |
| 其它名称： | AS5040-ASSTDKR |
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AS5040
Data Sheet
The angular displacement ( Θ ) of the magnetic source with reference to the Hall sensor array may then be modelled
( Y 1 ? Y 2 ) ± 0 . 5 °
by:
Θ = arctan
( X 1 ? X 2 )
The ± 0.5° angular error assumes a magnet optimally aligned over the center of the die and is a result of gain
mismatch errors of the AS5040. Placement tolerances of the die within the package are ± 0.235mm in X and Y
direction, using a reference point of the edge of pin #1 (Figure 23).
In order to neglect the influence of external disturbing magnetic fields, a robust differential sampling and ratiometric
calculation algorithm has been implemented. The differential sampling of the sine and cosine vectors removes any
common mode error due to DC components introduced by the magnetic source itself or external disturbing magnetic
fields. A ratiometric division of the sine and cosine vectors removes the need for an accurate absolute magnitude of
the magnetic field and thus accurate Z-axis alignment of the magnetic source.
The recommended differential input range of the magnetic field strength (B (X1-X2) ,B (Y1-Y2) ) is ± 75mT at the surface of
the die. In addition to this range, an additional offset of ± 5mT, caused by unwanted external stray fields is allowed.
The chip will continue to operate, but with degraded output linearity, if the signal field strength is outside the
recommended range. Too strong magnetic fields will introduce errors due to saturation effects in the internal
preamplifiers. Too weak magnetic fields will introduce errors due to noise becoming more dominant.
17 Failure Diagnostics
The AS5040 also offers several diagnostic and failure detection features:
Magnetic Field Strength Diagnosis
By software: the MagINCn and MagDECn status bits will both be high when the magnetic field is out of range.
By hardware: Pins #1 (MagINCn) and #2 (MagDECn) are open-drain outputs and will both be turned on (= low with
external pull-up resistor) when the magnetic field is out of range. If only one of the outputs is low, the magnet is either
moving towards the chip (MagINCn) or away from the chip (MagDECn).
Power Supply Failure Detection
By software: If the power supply to the AS5040 is interrupted, the digital data read by the SSI will be all “0”s. Data is
only valid, when bit OCF is high, hence a data stream with all “0”s is invalid. To ensure adequate low levels in the
failure case, a pull-down resistor (~10k Ω ) should be added between pin DO and VSS at the receiving side.
By hardware: The MagINCn and MagDECn pins are open drain outputs and require external pull-up resistors. In
normal operation, these pins are high ohmic and the outputs are high (see Table 3). In a failure case, either when the
magnetic field is out of range or the power supply is missing, these outputs will become low. To ensure adequate low
levels in case of a broken power supply to the AS5040, the pull-up resistors (>10k Ω ) from each pin must be
connected to the positive supply at pin 16 (VDD5V).
By hardware: PWM output: The PWM output is a constant stream of pulses with 1kHz repetition frequency. In case of
power loss, these pulses are missing.
By hardware: Incremental outputs: In normal operation, pins A(#3), B(#4) and Index (#6) will never be high at the
same time, as Index is only high when A=B=low. However, after a power-on-reset, if VDD is powered up or restarts
after a power supply interruption, all three outputs will remain in high state until pin CSn is pulled low. If CSn is
already tied to VSS during power-up, the incremental outputs will all be high until the internal offset compensation is
finished (within t PwrUp ).
www.austriamicrosystems.com
Revision 2.10
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