- 您现在的位置：买卖IC网 > PDF目录166232 > AS5LC512K8F-20L/XT (AUSTIN SEMICONDUCTOR INC) 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT PDF资料下载
参数资料
| 型号： | AS5LC512K8F-20L/XT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT |
| 中文描述： | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| 封装： | CERAMIC, DFP-36 |
| 文件页数： | 8/12页 |
| 文件大小： | 359K |
| 代理商： | AS5LC512K8F-20L/XT |
SRAM
AS5LC512K8
AS5LC512K8
Rev. 1.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
Austin Semiconductor, Inc.
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS (GND).
2.
I
CC limit shown is for absolute worst case switching of
ADDR, ADDR\, ADDR, etc.
3.
I
CC is dependent on output loading and cycle rates.
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7.
At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
AC TEST CONDITIONS
DESCRIPTION
SYM
MIN
MAX
UNITS
NOTES
Vcc for Retention Data
VDR
2V
Data Retention Current
Vcc = 2.0V
ICCDR
6.5
mA
Chip Deselect to Data
tCDR
0ns
4
Operation Recovery Time
tR
20
ms
4, 11
CONDITIONS
CE\ > VCC -0.2V
VIN > VCC -0.2 or 0.2V
3.3V
Q
353
5 pF
319
Q
30 pF
R
L
= 50
V
L
= 1.5V
Z
O=50
相关PDF资料 |
PDF描述 |
|---|---|
| AS5LC512K8F-20P/883C | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| AS5SS128K36DQ-11/IT | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS128K36DQ-11/XT | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS128K36DQ-12/IT | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS128K36DQ-12/XT | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5LC512K8F-25L/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT |
| AS5LC512K8F-25L/IT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT |
| AS5LC512K8F-25L/XT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT |
| AS5R100J | 功能描述:线绕电阻器 - 透孔 .1 OHM 5% 5W RoHS:否 制造商:Bourns 电阻:10 Ohms 容差:5 % 功率额定值:7 W 温度系数:200 PPM / C 系列:FW 端接类型:Axial 工作温度范围:- 55 C to + 155 C 尺寸:9.5 mm Dia. x 26 mm L 封装:Ammo 产品:Power Resistors Wirewound High Energy |
| AS5R100JLF | 制造商:TT Electronics / IRC 功能描述:AS5R100JLF |
发布紧急采购，3分钟左右您将得到回复。