参数资料
型号: AS5SS128K36DQ-11/XT
厂商: AUSTIN SEMICONDUCTOR INC
元件分类: SRAM
英文描述: 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT
中文描述: 128K X 36 ZBT SRAM, 8.5 ns, PQFP100
封装: TQFP-100
文件页数: 15/16页
文件大小: 119K
代理商: AS5SS128K36DQ-11/XT
SSRAM
AS5SS128K36
AS5SS128K36
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply Relative to V
SS
.................-0.5V to +4.6V
Voltage on V
DD
Q Supply Relative to V
SS
.................-0.5V to V
DD
V
IN
.................................................................. -0.5V to V
DD
Q +0.5V
Storage Temperature (Plastics) ..........................-55
°C to +150°C
Short Circuit Output Current ........................…..................100mA
Max. Junction Temperature*.............................................+150
°C
*Stresses greater than those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operation section of this speci-
fication is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
**Junction Temperature depends upon package type, cycle time, load-
ing, ambient temperture and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < T
A
< +125oC; V
DD,
V
DD
Q = +3.3V +0.165V unless otherwise noted)
NOTE:
1.
All voltages referenced to V
SS
(GND).
2.
Overshoot:
V
IH
< +4.6V for t < t
KHKH
/2 for I < 20mA.
Undershoot: V
IL
< -0.7V for t < t
KHKH
/2 for I < 20mA.
Power-up: V
IH
< +3.465V and V
DD
< 3.135V for t < 200ms.
3.
MODE pin has an internal pull-up, and input leakage = + 10
A.
4.
The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curvers
are available upon request.
5.
V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q should be externally wired together to the same power supply.
6.
This parameter is sampled.
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH
2.0
VDD + 0.3
V
1, 2
Input High (Logic 1) Voltage
DQ Pins
VIH
2.0
VDD + 0.3
V
1, 2
Input Low (Logic 0) Voltage
VIL
-0.3
0.8
V
1, 2
Input Leakage Current
0V < VIN < VDD
ILI
-1.0
1.0
A3
Output Leakage Current
Output(s) Disabled,
0V < VIN < VDD
ILO
-1.0
1.0
A
Output High Voltage
IOH = -4.0mA
VOH
2.4
---
V
1, 4
Output Low Voltage
IOL = 8.0mA
VOL
---
0.4
V
1, 4
Supply Voltage
VDD
3.135
3.465
V
1
Isolated Output Buffer Supply
VDDQ
3.135
VDD
V
1, 5
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
CI
34
pF
6
Input/Output Capacitance (DQ)
CO
45
pF
6
Address Capacitance
CA
3
3.5
pF
6
Clock Capacitance
CCK
3
3.5
pF
6
TA = 25
oC; f = 1 MHz
VDD = 3.3V
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