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参数资料
| 型号： | AS5SS128K36DQ-12/IT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| 中文描述： | 128K X 36 ZBT SRAM, 9 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 2/16页 |
| 文件大小： | 119K |
| 代理商： | AS5SS128K36DQ-12/IT |
SSRAM
AS5SS128K36
AS5SS128K36
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Austin Semiconductor, Inc.
DESCRIPTION
SYM
MIN
MAX
MIN
MAX
UNITS
NOTES
CLOCK
Clock cycle time
tKHKH
11
12
ns
Clock frequency
tKF
90
83
MHz
Clock HIGH time
tKHKL
3.0
ns
1
Clock LOW time
tKLKH
3.0
ns
1
OUTPUT TIMES
Clock to output valid
tKHQV
8.5
9.0
ns
Clock to output invalid
tKHQX
3.0
ns
2
Clock to output in Low-Z
tKHQX1
3.0
ns
2, 3, 4, 5
Clock to output in High-Z
tKHQZ
5.0
ns
2, 3, 4, 5
OE\ to output valid
tGLQV
5.0
ns
6
OE\ to output in Low-Z
tGLQX
0
ns
2, 3, 4, 5
OE\ to output in High-Z
tGHQZ
5.0
ns
2, 3, 4, 5
SETUP TIMES
Address
tAVKH
2.2
2.5
ns
7
Clock enable (CKE\)
tEVKH
2.2
2.5
ns
7
Control signals
tCVKH
2.2
2.5
ns
7
Data-in
tDVKH
2.2
2.5
ns
7
HOLD TIMES
Address
tKHAX
0.5
ns
7
Clock enable (CKE\)
tKHEX
0.5
ns
7
Control signals
tKHCX
0.5
ns
7
Data-in
tKHDX
0.5
ns
7
-11
-12
AC ELECTRICAL CHARACTERISTICS 6, 8, 9
(-55oC < T
A
< +125oC; V
DD,
V
DD
Q = +3.3V +0.165V)
NOTE:
1 .
Measured as HIGH above V
IH and LOW below VIL.
2 .
Contact ASI for more information on these parameters.
3.
This parameter is sampled.
4.
This parameter is measured with the output loading shown in Figure 2.
5 .
Transistion is measured +200mV from steady state voltage.
6 .
OE\ can be considerted a “Don’t Care” during WRITEs; however, controlling OE\ can help fine-tune a system for ZBL timing.
7 .
This is a synchrnous device. All addresses must meet the specified setup and hold times for all rising edgges o CLK when they are being
registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of
clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD\ is LOW to remain enabled.
8 .
Test conditions as specified with the output loading shown in Figure 1, unless otherwise noted.
9 .
A WRITE cycle is defined by R/W\ LOW having been registered into the device at ADV/LD\ LOW. A READ cycle is defined by R/W\
HIGH with ADV/LD\ LOW. Both cases must meet setup and hold times.
相关PDF资料 |
PDF描述 |
|---|---|
| AS5SS128K36DQ-12/XT | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS256K18DQ-10/IT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-10/XT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-9/IT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-9/XT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5SS128K36DQ-12XT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-9 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS256K18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256K x 18 SSRAM Synchronous Burst SRAM. Flow-Through |
| AS5SS256K18_05 | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
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