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参数资料
| 型号： | AS7C33512PFS32A-225TQC |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 STANDARD SRAM, 6.9 ns, PQFP100 |
| 封装： | 14 X 20 MM, TQFP-100 |
| 文件页数： | 4/21页 |
| 文件大小： | 463K |
| 代理商： | AS7C33512PFS32A-225TQC |
AS7C33512PFS32A
AS7C33512PFS36A
12/2/02, v. 0.9.8 Advance Info
Alliance Semiconductor
12 of 21
Reserved
Do not use a reserved instruction. These instructions are not implemented but are reserved for future use.
TAP timing diagram
TAP AC electrical characteristics
For notes 1 and 2, +10oC
≤ T
J ≤ +110
oC and +2.4V
≤ V
DD ≤ +2.6V.
Description
Symbol
Min
Max
Units
Clock
Clock cycle time
tTHTH
100
ns
Clock frequency
fTF
10
MHz
Clock high time
tTHTL
40
ns
Clock low time
tTLTH
40
ns
Output Times
TCK low to TDO unknown
tTLOX
0
ns
TCK low to TDO valid
tTLOV
20
ns
TDI valid to TCK high
tDVTH
10
ns
TCK high to TDI invalid
tTHDX
10
ns
Setup Times
TMS setup
tMVTH
10
ns
Capture setup
tCS1
1 tCS and tCH refer to the setup and hold time requirements of latching data
from the boundary scan register.
2 Test conditions are specified using the load in the figure TAP AC output
load equivalent.
10
ns
Hold Times
TMS hold
tTHMX
10
ns
Capture hold
tCH1
10
ns
W7+7/
W7/7+
W7+7+
W097+ W7+0;
W'97+ W7+';
W7/2;
W7/29
7HVW&ORFN
7&.
7HVW 0RGH 6HOHFW
706
7HVW'DWD,Q
7',
7HVW'DWD2XW
7'2
'RQWFDUH
8QGHILQHG
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C33512PFS36A-133TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
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