参数资料
型号: AT25F1024AN-10SU-2.7
厂商: Atmel
文件页数: 1/20页
文件大小: 0K
描述: IC FLASH 1MBIT 33MHZ 8SOIC
标准包装: 100
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 1M (128K x 8)
速度: 33MHz
接口: SPI 3 线串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
其它名称: AT25F1024AN10SU27
Features
? Serial Peripheral Interface (SPI) Compatible
? Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
? 33 MHz Clock Rate
? Byte Mode and 256-byte Page Mode for Program Operations
? Sector Architecture:
– Four Sectors with 32K Bytes Each (1M)
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– 128 Pages per Sector
Product Identification Mode
Low-voltage Operation
– 2.7 (V CC = 2.7V to 3.6V)
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (20 μ s/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
– Endurance: 10,000 Write Cycles Typical
– Data Retention: 20 Years
Lead-free/Halogen-free Devices
8-lead JEDEC SOIC and 8-lead SAP Packages
1Mbit High
Speed SPI
Serial Flash
Memory
1M (131,072 x 8)
AT25F1024A
Description
The AT25F1024A provides 1,048,576 bits of serial reprogrammable Flash memory
organized as 131,072 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F1024A is available in a space-saving 8-lead JEDEC SOIC
and 8-lead SAP packages.
The AT25F1024A is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All write cycles are completely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array is enabled by
programming the status register. Separate write enable and write disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Rev. 3346G–SFLSH–7/07
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