参数资料
型号: AT28BV64-30PI
厂商: Atmel
文件页数: 4/15页
文件大小: 0K
描述: IC EEPROM 64KBIT 300NS 28DIP
标准包装: 14
格式 - 存储器: EEPROMs - 并行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 300ns
接口: 并联
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.600",15.24mm)
供应商设备封装: 28-PDIP
包装: 管件
其它名称: AT28BV6430PI
5. Device Operation
5.1
5.2
5.3
5.4
Read
Byte Write
READY/BUSY
DATA Polling
The AT28BV64 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
Writing data into the AT28BV64 is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address loca-
tion is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of t WC , a read operation will effectively be a polling operation.
Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
The AT28BV64 provides DATA Polling to signal the completion of a write cycle. During a write
cycle, an attempted read of the data being written results in the complement of that data for I/O 7
(the other outputs are indeterminate). When the write cycle is finished, true data appears on all
outputs.
5.5
4
Write Protection
Inadvertent writes to the device are protected against in the following ways: (a) V CC sense – if
V CC is below 1.8V (typical) the write function is inhibited; (b) V CC power on delay – once V CC has
reached 2.0V the device will automatically time out 10 ms (typical) before allowing a byte write;
and (c) Write Inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
AT28BV64
0493C–PEEPR–08/07
相关PDF资料
PDF描述
AT28BV64-30JI IC EEPROM 64KBIT 300NS 32PLCC
356-010-525-102 CARDEDGE 10POS .156 BLACK
356-010-525-101 CARDEDGE 10POS .156 BLACK
356-010-521-104 CARDEDGE 10POS .156 BLACK
356-010-521-102 CARDEDGE 10POS .156 BLACK
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