参数资料
| 型号： | AT28C64B-15TU |
| 厂商： | Atmel |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 150NS 28TSOP |
| 标准包装： | 234 |
| 格式 - 存储器： | EEPROMs - 并行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 150ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-TSSOP（0.465"，11.8mm 宽） |
| 供应商设备封装： | 28-TSOP |
| 包装： | 托盘 |
| 产品目录页面： | 1458 (CN2011-ZH PDF) |
AT28C64B
3. Block Diagram
VCC
GND
DATA INPUTS/OUTPUTS
I/O0 - I/O7
OE
WE
OE, CE and WE
LOGIC
DATA LATCH
INPUT/OUTPUT
CE
ADDRESS
INPUTS
Y DECODER
BUFFERS
Y-GATING
CELL MATRIX
X DECODER
IDENTIFICATION
4. Device Operation
4.1
4.2
4.3
Read
Byte Write
Page Write
The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high-impedance state when either CE or OE is high. This dual line
control gives designers flexibility in preventing bus contention in their systems.
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of t WC , a read operation will effectively be a polling operation.
The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 μs (t BLC ) of the previous byte.
If the t BLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
3
0270L–PEEPR–2/09
相关PDF资料 |
PDF描述 |
|---|---|
| AT28C64B-15PU | IC EEPROM 64KBIT 150NS 28DIP |
| AT28C64B-15JU | IC EEPROM 64KBIT 150NS 32PLCC |
| AGLP060V2-VQG176I | IC FPGA IGLOO PLUS 60K 176-VQFN |
| AGLP060V2-VQ176I | IC FPGA IGLOO PLUS 60K 176-VQFN |
| AT28HC64BF-12SU | IC EEPROM 64KBIT 120NS 28SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT28C64B-15TU SL383 | 制造商:Atmel Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 5V 28TSOP-I - Tape and Reel |
| AT28C64B-15TU-T | 功能描述:150NS, TSOP, IND TEMP, GREEN 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:在售 存储器类型:非易失 存储器格式:EEPROM 技术:EEPROM 存储容量:64Kb （8K x 8） 写周期时间 - 字，页:10ms 访问时间:150ns 存储器接口:并联 电压 - 电源:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:28-TSSOP（0.465"，11.80mm 宽） 供应商器件封装:28-TSOP 标准包装:1 |
| AT28C64B-15UM/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 EEPROM |
| AT28C64B-20 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:64K (8K x 8) CMOS E2PROM with Page Write and Software Data Protection |
| AT28C64B-20DC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 EEPROM |
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