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| 型号： | AT32AP7002-CTUT |
| 厂商： | Atmel |
| 文件页数： | 38/83页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT AVR32 196-CBGA |
| 产品培训模块： | MCU Product Line Introduction |
| 标准包装： | 945 |
| 系列： | AVR®32 AP7 |
| 核心处理器： | AVR |
| 芯体尺寸： | 32-位 |
| 速度： | 150MHz |
| 连通性： | EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB |
| 外围设备： | AC'97，DMA，I²S，LCD，POR，PWM，WDT |
| 输入/输出数： | 85 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 数据转换器： | D/A 2x16b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 196-CBGA |
| 包装： | 托盘 |
| 配用： | ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR ATNGW100-ND - KIT AVR32 NETWORK GATEWAY ATSTK1000-ND - KIT STARTER FOR AVR32AP7000 |
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2011 Microchip Technology Inc.
DS70118J-page 35
dsPIC30F2010
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the effective
address calculation associated with any W register. It is
important to realize that the address boundaries check
for addresses less than or greater than the upper (for
incrementing buffers) and lower (for decrementing buf-
fers) boundary addresses (not just equal to). Address
changes may, therefore, jump beyond boundaries and
still be adjusted correctly.
4.3
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1.
BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not
be
accessed
using
Bit-Reversed
Addressing) and
2.
the BREN bit is set in the XBREV register and
3.
the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word-sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be gener-
ated instead. When Bit-Reversed Addressing is active,
the W Address Pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word-sized data is a requirement, the
LSb of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
FIGURE 4-2:
BIT-REVERSED ADDRESS EXAMPLE
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
Note:
All Bit-Reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
Modulo addressing and Bit-Reversed
Addressing
should
not
be
enabled
together. In the event that the user
attempts to do this, bit reversed address-
ing will assume priority when active for the
X WAGU, and X WAGU Modulo Address-
ing will be disabled. However, Modulo
Addressing will continue to function in the
X RAGU.
b3 b2 b1
0
b2 b3 b4
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4
b11 b10 b9 b8
b15 b14 b13 b12
Sequential Address
Pivot Point
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