参数资料
型号: AT32AP7002-CTUT
厂商: Atmel
文件页数: 73/83页
文件大小: 0K
描述: IC MCU 32BIT AVR32 196-CBGA
产品培训模块: MCU Product Line Introduction
标准包装: 945
系列: AVR®32 AP7
核心处理器: AVR
芯体尺寸: 32-位
速度: 150MHz
连通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外围设备: AC'97,DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 85
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: D/A 2x16b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 196-CBGA
包装: 托盘
配用: ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
2011 Microchip Technology Inc.
DS70118J-page 67
dsPIC30F2010
11.0
INPUT CAPTURE MODULE
This section describes the Input Capture module and
associated operational modes. The features provided
by this module are useful in applications requiring Fre-
quency (Period) and Pulse measurement. Figure 11-1
depicts a block diagram of the Input Capture module.
Input capture is useful for such modes as:
Frequency/Period/Pulse Measurements
Additional sources of External Interrupts
The key operational features of the Input Capture
module are:
Simple Capture Event mode
Timer2 and Timer3 mode selection
Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where
x = 1,2,...,N). The dsPIC DSC devices contain up to
eight capture channels, (i.e., the maximum value of
N is 8).
FIGURE 11-1:
INPUT CAPTURE MODE BLOCK DIAGRAM
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note:
The
dsPIC30F2010
device
has
four
capture inputs – IC1, IC2, IC7 and IC8.
The naming of these four capture chan-
nels is intentional and preserves software
compatibility
with
other
dsPIC
DSC
devices.
ICxBUF
Prescaler
ICx
ICM<2:0>
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N.
10
Set Flag
Pin
ICxIF
ICTMR
T2_CNT
T3_CNT
Edge
Detection
Logic
Clock
Synchronizer
1, 4, 16
From General Purpose Timer Module
16
FIFO
R/W
Logic
ICI<1:0>
ICBNE, ICOV
ICxCON
Interrupt
Logic
Set Flag
ICxIF
Data Bus
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