参数资料
型号: AT32UC3A464-C1UR
厂商: Atmel
文件页数: 75/94页
文件大小: 0K
描述: IC MCU 64K FLASH 100VFBGA
产品培训模块: AVR® UC3 Introduction
标准包装: 1
系列: AVR®32 UC3 A4
核心处理器: AVR
芯体尺寸: 32-位
速度: 66MHz
连通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,WDT
输入/输出数: 88
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-VFBGA
包装: 标准包装
其它名称: AT32UC3A464-C1URDKR
77
32072SH–AVR32–10/2012
AT32UC3A3
10.1.10
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
10.1.11
HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
10.1.12
TWIM
TWIM SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
10.1.13
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
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