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参数资料
| 型号： | AT45DB081D-SSU |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 8-megabit 2.5-volt or 2.7-volt DataFlash |
| 中文描述： | 8M X 1 FLASH 2.7V PROM, PDSO8 |
| 封装： | 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件页数： | 7/53页 |
| 文件大小： | 1105K |
| 代理商： | AT45DB081D-SSU |
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3596E–DFLASH–02/07
AT45DB081D
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page).
W
hen the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
6.4
Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 4,096 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and 4 don’t care bytes. The first 12 bits (PA11 - PA0) of
the 21-bit address sequence specify the page in main memory to be read, and the last 9 bits
(BA8 - BA0) of the 21-bit address sequence specify the starting byte address within that page.
To start a page read from the binary page size (256 bytes), the opcode D2H must be
clocked into the device followed by three address bytes and 4 don’t care bytes. The first 12 bits
(A19 - A8) of the 20-bits sequence specify which page of the main memory array to read, and
the last 8 bits (A7 - A0) of the 20-bits address sequence specify the starting byte address within
the page. The don’t care bytes that follow the address bytes are sent to initialize the read opera-
tion. Following the don’t care bytes, additional pulses on SCK result in data being output on the
SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data.
W
hen the end of a page in main
memory is reached, the device will continue reading back at the beginning of the same page. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin
(SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the
f
SCK
specification. The Main Memory Page Read bypasses both data buffers and leaves the con-
tents of the buffers unchanged.
6.5
Buffer Read
The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four
opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read
Command. The use of each opcode depends on the maximum SCK frequency that will be used
to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to
the maximum specified by f
CAR1
. The D1H and D3H opcode can be used for lower frequency
read operations up to the maximum specified by f
CAR2
.
To perform a buffer read from the standard DataFlash buffer (264 bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 15 don’t care bits and
9 buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256 bytes),
the opcode must be clocked into the device followed by three address bytes comprised of
16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one
don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low
during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data.
W
hen the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
相关PDF资料 |
PDF描述 |
|---|---|
| AT45DB081D-SSU-2.5 | 8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D-SU | 8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D-SU-2.5 | 8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081 | 8-Megabit 2.7-volt Only Serial DataFlash |
| AT45DB081-RC | 8-Megabit 2.7-volt Only Serial DataFlash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT45DB081D-SSU SL383 | 制造商:Adesto Technologies 功能描述:Fuse Blade 4A 90V Slow Blow 2-Pin Lug Socket 制造商:Adesto Technologies Corporation 功能描述:DATAFLASH,8MBIT,SERIAL,2.7V,IND TEMP,GRN SOIC 150 - Tape and Reel |
| AT45DB081D-SSU SL383-AD | 功能描述:DATA FLASH 制造商:adesto technologies 系列:- 包装:剪切带（CT） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:8Mb （264 字节 x 4096 页） 时钟频率:66MHz 写周期时间 - 字，页:4ms 存储器接口:SPI 电压 - 电源:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商器件封装:8-SOIC 标准包装:1 |
| AT45DB081D-SSU SL594 | 制造商:Adesto Technologies Corporation 功能描述: |
| AT45DB081D-SSU SL954 | 制造商:Adesto Technologies Corporation 功能描述:DATAFLASH,8MBIT,SERIAL,2.7V,IND TEMP,GRN SOIC 150 - Rail/Tube |
| AT45DB081D-SSU SL955 | 制造商:Adesto Technologies Corporation 功能描述:DATAFLASH - Rail/Tube |
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