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参数资料
| 型号： | AT49BV802AT-70CI |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 8-megabit (512K x 16/ 1M x 8) 3-volt Only Flash Memory |
| 中文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PBGA48 |
| 封装： | 6 X 8 MM, 1 MM HIEGHT, 0.80 MM PITCH, PLASTIC, CBGA-48 |
| 文件页数： | 4/29页 |
| 文件大小： | 253K |
| 代理商： | AT49BV802AT-70CI |
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4
AT49BV802A(T)
3405C–FLASH–9/04
CHIP ERASE:
The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t
EC
.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE:
As an alternative to a full chip erase, the device is organized into 23 sec-
tors (SA0 - SA22) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is t
SEC
. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating immediately.
BYTE/WORD PROGRAMMING:
Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automati-
cally generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
BP
cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
PROGRAM/ERASE STATUS:
The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 10 and
the following four sections describe the function of these bits. To provide greater flexibility for
system designers, the AT49BV802A(T) contains a programmable configuration register. The
configuration register allows the user to specify the status bit operation. The configuration reg-
ister can be set to one of two different values, “00” or “01”. If the configuration register is set to
“00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 11, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
相关PDF资料 |
PDF描述 |
|---|---|
| AT49BV802AT-70TI | 8-megabit (512K x 16/ 1M x 8) 3-volt Only Flash Memory |
| AT49BV8192A-12CI | 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory |
| AT49BV8192A-12TC | 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory |
| AT49BV8192A-12TI | 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory |
| AT49BV8192A-15CC | 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT49BV802AT-70CI SL383 | 功能描述:IC FLASH 8MBIT 70NS 48CBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
| AT49BV802AT-70CI-T | 功能描述:IC FLASH 8MBIT 70NS 48CBGA 制造商:microchip technology 系列:- 包装:带卷（TR） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:8Mb （1M x 8，512K x 16） 写周期时间 - 字，页:200μs 访问时间:70ns 存储器接口:并联 电压 - 电源:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:48-VFBGA，CSBGA 供应商器件封装:48-CBGA（6x8） 基本零件编号:AT49BV802 标准包装:2,500 |
| AT49BV802AT-70CU | 功能描述:闪存 8M TOP BOOT-PKG- 8M TOP BOOT RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49BV802AT-70TI | 功能描述:闪存 8M TOP BOOT-PKG- 8M TOP BOOT RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49BV802AT-70TI SL383 | 功能描述:IC FLASH 8MBIT 70NS 48TSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
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