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参数资料
| 型号： | AT49F040A-70TI |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 4-megabit (512K x 8) 5-volt Only Flash Memory |
| 中文描述： | 512K X 8 FLASH 5V PROM, 70 ns, PDSO32 |
| 封装： | 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32 |
| 文件页数： | 3/16页 |
| 文件大小： | 248K |
| 代理商： | AT49F040A-70TI |
3
AT49F040A
3359B–FLASH–10/04
Device
Operation
READ:
The AT49F040A is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins is asserted on
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES:
When the device is first powered on, it will be reset to the read or
standby mode depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table. The command sequences are written
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.
The address locations used in the command sequences are not affected by entering the com-
mand sequences.
ERASURE:
Before a byte can be reprogrammed, the main memory block or parameter block
which contains the byte must be erased. The erased state of the memory bits is a logical “1”.
The entire device can be erased at one time by using a 6-byte software code. The software
chip erase code consists of 6-byte load commands to specific address locations with a specific
data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are required. The maximum time needed to erase the whole
chip is t
EC
. If the boot block lockout feature has been enabled, the data in the boot sector will
not be erased.
CHIP ERASE:
If the boot block lockout has been enabled, the Chip Erase function will erase
Parameter Block 1, Parameter Block 2, Main Memory Block 1 - 8 but not the boot block. If the
Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip.
After the full chip erase the device will return back to read mode. Any command during chip
erase will be ignored.
SECTOR ERASE:
As an alternative to a full chip erase, the device is organized into sectors
that can be individually erased. There are two 8K-byte parameter block sections and eight
main memory blocks. The 8K-byte parameter block sections and the eight main memory
blocks can be independently erased and reprogrammed. The Sector Erase command is a six
bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle
while the 30H data input command is latched at the rising edge of WE. The sector erase starts
after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion.
BYTE PROGRAMMING:
Once the memory array is erased, the device is programmed (to a
logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to
a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle operation (please refer to the Command
Definitions table). The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Program-
ming is completed after the specified t
BP
cycle time. The DATA polling feature may also be
used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block that has
a programming lockout feature. This feature prevents programming of data in the designated
block once the feature has been enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that is used to bring up the system.
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| AT49F080T-12RC | 8-Megabit 1M x 8 5-volt Only Flash Memory |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT49F040A-70TI SL383 | 功能描述:IC FLASH 4MBIT 70NS 32TSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
| AT49F040A-70TI-T | 功能描述:IC FLASH 4MBIT 70NS 32TSOP 制造商:microchip technology 系列:- 包装:带卷（TR） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:4Mb （512K x 8） 写周期时间 - 字，页:40μs 访问时间:70ns 存储器接口:并联 电压 - 电源:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:32-TFSOP（0.724"，18.40mm 宽） 供应商器件封装:32-TSOP 基本零件编号:AT49F040 标准包装:1,500 |
| AT49F040A-70TU | 功能描述:IC FLASH 4MBIT 70NS 32TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
| AT49F040A-70TU SL383 | 功能描述:IC FLASH 4MBIT 70NS 32TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
| AT49F040A-70TU-T | 功能描述:IC FLASH 4MBIT 70NS 32TSOP 制造商:microchip technology 系列:- 包装:带卷（TR） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:4Mb （512K x 8） 写周期时间 - 字，页:40μs 访问时间:70ns 存储器接口:并联 电压 - 电源:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:32-TFSOP（0.724"，18.40mm 宽） 供应商器件封装:32-TSOP 基本零件编号:AT49F040 标准包装:1,500 |
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