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参数资料
| 型号： | AT6005LV-4JC |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | Coprocessor Field Programmable Gate Arrays |
| 中文描述： | FPGA, 3136 CLBS, 15000 GATES, PQCC84 |
| 封装： | PLASTIC, MS-018AF, LCC-84 |
| 文件页数： | 8/28页 |
| 文件大小： | 835K |
| 代理商： | AT6005LV-4JC |
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AT6000(LV) Series
8
Figure 11.
A-type I/O Logic
Figure 12.
B-type I/O Logic
TTL/CMOS Inputs
A user-configurable bit determines the threshold level
–
TTL or CMOS
–
of the input buffer.
Open Collector/Tristate Outputs
A user-configurable bit which enables or disables the active
pull-up of the output device.
Slew Rate Control
A user-configurable bit controls the slew rate
–
fast or slow
–
of the output buffer. A slow slew rate, which reduces
noise and ground bounce, is recommended for outputs that
are not speed-critical. Fast and slow slew rates have the
same DC-current sinking capabilities, but the rate at which
each allows the output devices to reach full drive differs.
Pull-up
A user-configurable bit controls the pull-up transistor in the
I/O pin. It
’
s primary function is to provide a logical
“
1
”
to
unused input pins. When on, it is approximately equivalent
to a 25K resistor to V
CC
.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static
–
always on or
always off
–
or dynamically controlled by a signal gener-
ated in the array. Four options are available from the array:
(1) the control is low and always driving; (2) the control is
high and never driving; (3) the control is connected to a ver-
tical local bus associated with the output cell; or (4) the
control is connected to a horizontal local bus associated
with the output cell. On power-up, the user I/Os are config-
ured as inputs with pull-up resistors.
In addition to the functionality provided by the I/O logic, the
entrance and exit cells provide the ability to register both
inputs and outputs. Also, these perimeter cells (unlike inte-
rior cells) are connected directly to express buses: the
edge-facing A and B outputs of the entrance cell are con-
nected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to the
edge, and provide a rapid means of bringing I/O signals to
and from the array interior and the opposite edge of the
chip.
Chip Configuration
The Integrated Development System generates the SRAM
bit pattern required to configure a AT6000 Series device. A
PC parallel port, microprocessor, EPROM or serial configu-
ration memory can be used to download configuration
patterns.
Users select from several configuration modes. Many fac-
tors, including board area, configuration speed and the
number of designs implemented in parallel can influence
the user
’
s final choice.
Configuration is controlled by dedicated configuration pins
and dual-function pins that double as I/O pins when the
device is in operation. The number of dual-function pins
required for each mode varies.
相关PDF资料 |
PDF描述 |
|---|---|
| AT6005LV-4QC | Coprocessor Field Programmable Gate Arrays |
| AT6010-2JC | Coprocessor Field Programmable Gate Arrays |
| AT6010-2JI | Coprocessor Field Programmable Gate Arrays |
| AT6010-2QC | Coprocessor Field Programmable Gate Arrays |
| AT6010-2QI | Coprocessor Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT6005LV-4QC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT-601(40) | 功能描述:衰减器 -互连 RoHS:否 制造商:Pomona Electronics 最大衰减: 容差: 频率范围:DC to 500 MHz 阻抗:50 Ohms 功率额定值:2 W 端接类型:Crimp 连接器类型:BNC Male / Female 工作温度范围:0 C to + 102 C |
| AT60100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | NPN | 8MA I(C) | CHIP |
| AT6010-2JC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6010-2JI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
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