参数资料
型号: AT73C209-EK
厂商: Atmel
文件页数: 40/63页
文件大小: 0K
描述: BOARD EVAL FOR AT73C209
标准包装: 1
系列: PMAAC™
主要目的: 电源管理,专用型: 手机
已用 IC / 零件: AT73C209
已供物品: 板,CD,文档
10.4
Data Interface
Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial
interface, as illustrated in the timing diagrams below. To avoid noise at the output, the reset state
is maintained until proper synchronization is achieved in the serial interface.
The data interface allows three different data transfer modes as described below.
Figure 10-2. 20-bit I2S Justified Mode
BCLK
LRFS
SDIN
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
Figure 10-3. 20-bit MSB Justified Mode
BCLK
LRFS
SDIN
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
Figure 10-4. 20-bit LSB Justified Mode
BCLK
LRFS
SDIN
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL<5:4> bits in the register 0x0A accord-
ing with the following table.
DINTSEL <5:4>
00
01
1x
Format
I2S Justified
MSB Justified
LSB Justified
The data interface always works in slave mode. This means that the LRFS and the BCLK sig-
nals are provided by the host controller. In order to achieve proper operation, the LRFS and the
BCLK signals must be synchronous with the MCLK master clock signal and their frequency rela-
tionship must reflect the selected data mode. For example, if the data mode selected is the 20-
bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.
40
AT73C209
6365A–PMAAC–12-Mar-08
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