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参数资料
| 型号： | AT76C651 |
| 厂商： | ATMEL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | Digital Reception/Transmission Integrated DVB compliant QAM Demodulator(兼容DVB的正交振幅调制解调电路) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 24/37页 |
| 文件大小： | 497K |
| 代理商： | AT76C651 |
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AT76C651
24
MASKLOCK1: 0x09 (read/write)
This register specifies the lock signals that must be moni-
tored on the LOCK1 output pin. If all internal lock signals
configured by this mask go high, then LOCK1 goes high.
b7
b6
b5
b4
fec: Mask on forward error correction lock signal
car: Mask on carrier recovery loop lock signal
equ: Mask on equalizer lock signal
tim: Mask on symbol rate recovery lock signal
agc2: Mask on digital agc lock signal
agc1: Mask on analog agc lock signal
adc: Mask on analog agc level lock signal
pll: Mask on Phase Locked Loop (PLL) lock signal
SETAUTOCFG configures MASKLOCK1 at value 0x80,
corresponding to the FEC lock signal only.
MASKLOCK2: 0x0A (read/write)
This register specifies the lock signals that must be moni-
tored on the LOCK2 output pin. If all internal lock signals
configured by this mask go high, then LOCK2 goes high.
b7
b6
b5
b4
SETAUTOCFG configures MASKLOCK2 at value 0x70,
corresponding to the lock signals of the carrier recovery,
the equalizer and the timing recovery, which is the full
demodulator.
IRQMASK: 0x0B (read/write)
Mask for IRQ output pin. This register specifies the mask
on events that should activate the IRQ pin. IRQ goes to the
value specified by irqpol (see OUTPUTCFG configuration)
when any of the events specified by the mask described
below occur and goes back to high impedance when any
I
2
C register is written by the microcontroller.
unlck1: IRQ when LOCK1 signal goes from 1 to 0
lck1: IRQ when LOCK1 signal goes from 0 to 1
unlck2: IRQ when LOCK2 signal goes from 1 to 0
lck2: IRQ when LOCK2 signal goes from 0 to 1
sat: IRQ when signal input loss (AGC saturation)
frmlst: IRQ when frame was lost
time_win: Periodic generation of IRQ
00: IRQ not activated by time delay
01: IRQ activated every 2048 frames
10: IRQ activated every 16384 frames
11: IRQ activated every 10
8
bits
SETAUTOCFG configures the mask on UNLOCK1.
TUNI2CADD: 0x0C (read/write)
I
2
C address of tuner when connected to I
2
C bus of device
(pins TI2CSCL and TI2CSDA). For more details on the
tuner I
2
C switch principle, see
“
I
2
C Read Mode
”
on page 9.
b7
b6
b5
b4
EN enables the switch when set to 1.
Note:
EN should be set to 1 when tuner is configured. Then EN
must be set back to 0.
CHIPID: 0x0E to 0x0F (read)
Gives information about chip number and version. Value is
0x6510 (AT76C651, version A).
b7
b6
b5
b4
Baseband Conversion and AGC1
AGC1NMIN: 0x13 (read/write)
Specifies the minimum (or maximum) amplification value of
AGC1 given by the PWM output pin, which is between 0
and 255 when BBCFG(4) = 0 or BBCFG(4) = 1. For more
details about the BBCFG register, see the description
below. This value can be used to saturate amplification in
case of non-linearities of the amplifier at extreme values.
Example:
0x00 (for maximum amplifying range)
fec
car
equ
tim
0x09
b3
b2
b1
b0
agc
2
agc
1
adc
pll
fec
car
equ
tim
0x0A
b3
b2
b1
b0
agc
2
agc
1
adc
pll
unlck
1
lck
1
unlck
2
lck
2
0x0A
b7
b6
b5
b4
b3
b2
b1
b0
frm
lst
sat
time_win
Tuner I
2
C address
0x0C
b3
b2
b1
b0
EN
0x0E
0x0F
b3
b2
b1
b0
0
1
1
0
0
1
0
1
0
0
0
1
0
0
0
0
agc1nmin
0x13
b7
b6
b5
b4
b3
b2
b1
b0
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