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参数资料
| 型号： | AT76C651 |
| 厂商： | ATMEL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | Digital Reception/Transmission Integrated DVB compliant QAM Demodulator(兼容DVB的正交振幅调制解调电路) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 30/37页 |
| 文件大小： | 497K |
| 代理商： | AT76C651 |
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AT76C651
30
FECINH: 0x65 (read/write)
Inhibition of selected parts of the forward error correction
blocks.
b7
b6
b5
b4
FECINH is a 7-bit value. Each bit set to 1 indicates that the
selected function is inhibited. The hardware block is then in
a transparent mode.
Example: For DVB MPEG2-TS, FECINH should be set to
0x00 (default value) but to execute an external bit error rate
measure, b3, b5 and b6 should probably be set to 1
(FECINH = 0x68).
For non-DVB applications, with FECINH = 0x7E, it is possi-
ble to get data after QAM de-mapping and differential
decoder in serial mode or in parallel mode (bytes are not
aligned).
PID Filtering
PID1: 0x70 to 0x71 (read/write)
First MPEG PID to filter. This function can be disabled.
b7
b6
b5
PID1 is a 14-bit value that gives the first MPEG PID to flag.
This function is provided to enable the use of a simple soft-
ware MPEG de-multiplexer. Bit 5 of the register 0x70 is an
enable. When this function is enabled and if the 13-bit PID
of an incoming frame matches PID1, the FLAGPID0 pin
takes the value 1 and the FLAGPID1 pin takes the value 0.
This filter has a higher priority than PID2 and PID3. The
default value is 0x0000 so the function is disabled.
PID2: 0x72 to 0x73 (read/write)
Second MPEG PID to filter. This function can be disabled.
b7
b6
b5
b4
PID2 is a 14-bit value that gives the second MPEG PID to
flag. This function is provided to enable the use of simple
software MPEG de-multiplexer. Bit 5 of the register 0x72 is
an enable. When this function is enabled, if the 13-bit PID
of an incoming frame matches PID2 and if PID1 flag is not
set, the FLAGPID1 pin takes the value 1 and the
FLAGPID0 pin takes the value 0. This filter has a higher pri-
ority than PID3, but lower than PID1. The default value is
0x0000, so the function is disabled.
PID3: 0x74 to 0x76 (read/write) and
PIDMSK3: 0x77to 0x79 (read/write)
Third PID to filter. This filter has a 24-bit length with a mask
of the same length.
b7
b6
b5
b4
PID3 is a 24-bit value that gives the third PID (the 2nd, 3rd
and 4th bytes of frame) to flag. This function is provided to
enable the use of a simple software MPEG de-multiplexer.
A 24-bit mask is also provided by registers 0x77 to 0x79.
The MPEG header bits are only checked with PID3 if the
corresponding bits in PIDMSK3 are set to 1. If PIDMSK3 is
set to 0x000000, the function is disabled.
If PID1 or PID2 get a match for a particular frame, PID3 fil-
ter is not performed for this frame. When PID3 gets a
match, both pins FLAGPID0 and FLAGPID1 are set to 1.
This filter has a lower priority than PID1 and PID2. The
default value is 0x000000 for PID3 and PIDMSK3. This
function is disabled.
Table 18.
FECINH
Bits
Functions Inhibited
Comments
b0: diff
differential decoder
useful for non-coherent
demodulation
b1: frm
frame
synchronization
prevent bit skipping if
frames not needed
b2: dilv
de-interleaver
cannot be synchronized
without frames
b3: rs
Reed-Solomon
decoder
error detection without
correction
b4: scrm
scrambler
need inverted FECFSW
for synchronization
b5: force
1st byte forced to
FECFSW
cannot be used without
frame recovery
b6: beind
Bit Error Indicator
(MSB of 2nd byte)
enable external bit error
rate measure
0x65
b3
b2
b1
b0
res
beind force
scrm
rs
dilv
frm
diff
reserved
enpid1
0x70
0x71
b4
b3
b2
b1
b0
pid1 (7:0)
pid1 (12:8)
reserved
enpid2
0x72
0x73
b3
b2
b1
b0
pid2 (7:0)
pid2 (12:8)
pid3 (23:16)
0x74
b3
b2
b1
b0
pid3 (15:8)
0x75
pid3 (7:0)
0x76
pidmsk3 (23:16)
0x77
pidmsk3 (15:8)
0x78
pidmsk3 (7:0)
0x79
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