- 您现在的位置：买卖IC网 > PDF目录381492 > AT80C51RB2-3CSIM (Atmel Corp.) 80C51 High Performance ROM 8-bit Microcontroller PDF资料下载
参数资料
| 型号： | AT80C51RB2-3CSIM |
| 厂商： | Atmel Corp. |
| 英文描述： | 80C51 High Performance ROM 8-bit Microcontroller |
| 中文描述： | 80C51的高性能ROM的8位微控制器 |
| 文件页数： | 60/83页 |
| 文件大小： | 672K |
| 代理商： | AT80C51RB2-3CSIM |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页当前第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
61
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. Therefore, the user must
reset the WDT at least every 16383 machine cycles. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
CLK PERIPH
, where T
CLK PERIPH
= 1/F
CLK
PERIPH
. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
7
counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ F
osc
= 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 44.
Table 44.
WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
相关PDF资料 |
PDF描述 |
|---|---|
| AT80C51RB2-3CSUM | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIL | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIM | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTUL | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTUM | 80C51 High Performance ROM 8-bit Microcontroller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT80C51RB2-3CSUM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTUL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTUM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
发布紧急采购，3分钟左右您将得到回复。