参数资料
| 型号： | AT80C51RD2-SLSUM |
| 厂商： | Atmel |
| 文件页数： | 55/81页 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU 5V SPI 20MHZ 44-PLCC |
| 标准包装： | 972 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-PLCC |
| 包装： | 管件 |
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59
4113D–8051–01/09
AT80C51RD2
Table 15-2.
WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
15.2
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as normal, whenever the AT80C51RD2 is reset. Exiting Power-down with an
interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabi-
lize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down, it is bet-
ter to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT80C51RD2 while in Idle mode, the user should always set up a timer that will periodically exit
Idle, service the WDT, and re-enter Idle mode.
76
543
210
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2
WDT Time-out select bit 2
1S1
WDT Time-out select bit 1
0S0
WDT Time-out select bit 0
S2S1 S0Selected Time-out
00
0
(214 - 1) machine cycles, 16. 3 ms @ F
osc =12 MHz
00
1
(2
15 - 1) machine cycles, 32.7 ms @ F
osc=12 MHz
01
0 (216 - 1) machine cycles, 65. 5 ms @ F
osc=12 MHz
01
1
(217 - 1) machine cycles, 131 ms @ F
osc=12 MHz
10
0
(2
18 - 1) machine cycles, 262 ms @ F
osc=12 MHz
10
1 (219 - 1) machine cycles, 542 ms @ F
osc=12 MHz
11
0
(220 - 1) machine cycles, 1.05 s @ F
osc=12 MHz
11
1
(2
21 - 1) machine cycles, 2.09 s @ F
osc=12 MHz
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