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参数资料
| 型号： | AT84AD001TD-EB |
| 厂商： | Atmel Corp. |
| 英文描述： | Dual 8-bit 1 Gsps ADC |
| 中文描述： | 双8位ADC的1 GSPS的 |
| 文件页数： | 38/60页 |
| 文件大小： | 1343K |
| 代理商： | AT84AD001TD-EB |
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38
AT84AD001B
2153C–BDC–04/04
Notes:
1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and Q) of the
sample/hold (with a fixed digital sampling time) with steps of ±50 ps:
Nominal mode will be given by Data2…Data0 = 100 or Data5…Data3 = 100.
Data5…Data3 = 000 or Data2…Data0 = 000: sampling time is -200 ps compared to nominal.
Data2…Data0 = 111 or Data5…Data3 = 111: sampling time is 150 ps compared to nominal.
We recommend setting the ISA to -50 ps to optimize the ADC’s dynamic performances.
2. The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of ±5 ps) on channel Q more pre-
cisely, particularly in the interleaved mode.
3. A Built-In Test (BIT) function is available to rapidly test the device’s I/O by either applying a defined static pattern to the dual
ADC or by generating a dynamic ramp at the output of the dual ADC. This function is controlled via the 3-wire bus interface
at the address 110. The maximum clock frequency in dynamic BIT mode is 750 Msps.
Please refer to “Built-In Test (BIT)” on page 43 for more information about this function.
4. The decimation mode enables you to lower the output bit rate (including the output clock rate) by a factor of 16, while the
internal clock frequency remains unchanged. The maximum clock frequency in decimation mode is 750 Msps.
5. The “S/H transparent” mode (address 101, Data4) enables bypassing of the ADC’s track/hold. This function optimizes the
ADC’s performances at very low input frequencies (Fin < 50 MHz).
6. In the Gray mode, when the input signal is overflow (that is, the differential analog input is greater than 250 mV), the output
data must be corrected using the output DOIR:
If DOIR = 1: Data7 unchanged
Data6 = 0, Data5 = 0, Data4 = 0, Data3 = 0, Data2 = 0, Data1 = 0, Data0 = 0.
In 1:2 DMUX mode, only one out-of-range bit is provided for both A and B ports.
101
Testability
Data3 to Data0 = 0000
Mode S/H transparent
Data7 = 0
Data8 = 0
Built-In Test (BIT)
Data0 = 0
Data1 = 0
If Data1 = 1, then Ports BI & BQ = Rising Ramp
Ports AI & AQ = Decreasing Ramp
If Data1 = 0, then Data2 to Data9 = Static Data for BIT
Ports BI & BQ = Data2 to Data9
Ports AI & AQ = NOT (Data2 to Data9)
Data Ready Delay Adjust (DRDA)
Data2 to Data0: clock I
Data5 to Data3: clock Q
Steps: 140 ps
000: -560 ps
100: 0 ps
111: 420 ps
OFF: Data4 = 0
ON: Data4 = 1
110
BIT Inactive
Static BIT
Data0 = 1
Data1 = 1
BIT Active
Dynamic BIT
111
Fine Sampling Delay Adjustment (FiSDA) on channel Q
Data10 to Data6: channel Q
Steps: 5 ps
Data4: sign bit
Code 11111: -75 ps
Code 10000: 0 ps
Code 00000: 0 ps
Code 01111: 75 ps
Table 12.
3-wire Serial Interface Address Setting Description (Continued)
Address
Setting
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