- 您现在的位置：买卖IC网 > PDF目录381497 > AT84AD004VTD (ATMEL CORP) DUAL 8 BIT 500 MSPS ADC PDF资料下载
参数资料
| 型号： | AT84AD004VTD |
| 厂商： | ATMEL CORP |
| 元件分类： | ADC |
| 英文描述： | DUAL 8 BIT 500 MSPS ADC |
| 中文描述： | 2-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | 20 X 20 MM, 1.4 MM HEIGHT, LQFP-144 |
| 文件页数： | 40/58页 |
| 文件大小： | 1023K |
| 代理商： | AT84AD004VTD |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页
40
AT84AD004
5390A–BDC–06/04
Calibration Description
The AT84AD004 offers the possibility of reducing offset and gain matching between the
two ADC cores. An internal digital calibration may start right after the 3-wire serial inter-
face has been loaded (using data D12 of the 3-wire serial interface with address 000).
The beginning of calibration disables the two ADCs and a standard data acquisition is
performed. The output bit CAL goes to a high level during the entire calibration phase.
When this bit returns to a low level, the two ADCs are calibrated with offset and gain and
can be used again for a standard data acquisition.
If only one channel is selected (I or Q) the offset calibration duration is divided by two
and no gain calibration between the two channels is necessary.
Figure 41.
Internal Timing Calibration
The Tcal duration is a multiple of the clock frequency ClockI (master clock). Even if a
dual clock scheme is used during calibration, ClockQ will not be used.
The control wait bits (D13 and D14) give the possibility of changing the calibration’s set-
ting depending on the clock’s frequency:
For high clock rates (= 500 Msps) use a = b = 1, Tcal = 10112 clock I periods.
For clock rates > 250 Msps and < 500 Msps use a = 1, b = 0, Tcal = 6016 clock I
periods.
For clock rates > 125 Msps and < 250 Msps use a = 0, b = 1 ,Tcal = 3968 clock I
periods.
For low clock rates (< 125 Msps) use a = 0, b = 0 , Tcal = 2944 clock I periods.
Table 12.
Timing Description
Name
Parameter
Value
Unit
Min
Typ
Max
Tsclk
Sclk period
20
ns
Twsclk
High or low time of sclk
5
ns
Tssldn
Setup time of sldn before rising edge of sclk
4
ns
Thsldn
Hold time of sldn after rising edge of sclk
2
ns
Tssdata
Setup time of sdata before rising edge of sclk
4
ns
Thsdata
Hold time of sdata after rising edge of sclk
2
ns
Twlmode
Minimum low pulse width of mode
5
ns
Tdmode
Minimum delay between an edge of mode and the
rising edge of sclk
10
ns
3-wire Serial Interface
LDN
CAL
Tcal
相关PDF资料 |
PDF描述 |
|---|---|
| AT84AS003VTP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84XAS003TP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003 | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003CTP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003TP-EB | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT84AS001CTPY | 制造商:e2v technologies 功能描述:ADC SGL 500MSPS 12-BIT LVDS 192PIN EBGA - Trays |
| AT84AS001TP-EB | 制造商:e2v technologies 功能描述:EVAL KIT FOR 12-BIT ADC - Bulk |
| AT84AS001VTPY | 制造商:e2v technologies 功能描述:ADC SGL 500MSPS 12-BIT LVDS 192PIN EBGA - Trays |
| AT84AS003 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003CTP | 功能描述:BROADBAND DATA CONVERTR EGBA 317 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
发布紧急采购，3分钟左右您将得到回复。