参数资料
| 型号： | AT88SA102S-TSU-T |
| 厂商： | Atmel |
| 文件页数： | 4/25页 |
| 文件大小： | 0K |
| 描述： | IC PROD AUTHENTICATION SOT23-3 |
| 产品培训模块： | CryptoAuthentication™ Introduction |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | AT88SA102S-TSU-TDKR |
12
5.3.1
IO Timeout
After a leading transition for any data token has been received, the AT88SA102S will expect the remaining bits of the token to
be properly received by the chip within the tTIMEOUT interval. Failure to send enough bits or the transmission of an illegal token
(a low pulse exceeding tZLO) will cause the chip to enter the sleep state after the tTIMEOUT interval.
The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the
IO Timeout circuitry is enabled until the last expected data bit is received.
Note:
The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the
tTIMEOUT interval while the time between bits may not.
In order to limit the active current if AT88SA102S is inadvertently awakened, the IO timeout circuitry is also enabled when
AT88SA102S receives a wake-up. If the first token does not come within the tTIMEOUT interval, then AT88SA102S will go back
to the sleep mode without performing any operations.
The IO timeout circuitry is disabled when the chip is busy executing a command.
5.3.2
Synchronization Procedures
When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a transmit flag
which will not generate a response from AT88SA102S. The system should implement its own timeout which waits for tTIMEOUT
during which time AT88SA102S should go to sleep automatically. At this point, the system should send a Wake token and
after tWLO + tWHI, a transmit token. The 0x11 status indicates that the resynchronization was successful.
It may be possible that the system does not get the 0x11 code from AT88SA102S for one of the following reasons:
1.
The system did not wait a full tTIMEOUT delay with the IO signal idle in which case AT88SA102S may have interpreted
the Wake token and transmit flag as data bits. Recommended resolution is to wait twice the tTIMEOUT delay and re-issue
the Wake token.
2.
AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case,
AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits
during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag,
though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a
correct CRC. Recommended resolution is to wait the tTIMEOUT delay and re-issue the Wake token.
3.
There is some internal error condition within AT88SA102S which will be automatically reset after a tWATCHDOG interval,
see Section 5.4. There is no way to externally reset AT88SA102S – the system should leave the IO pin idle for this
interval and issue the Wake token.
5.4
Watchdog Failsafe
After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After tWATCHDOG, the
chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO
transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low sleep level
automatically.
5.5
Byte and Bit Ordering
AT88SA102S is a little-endian chip:
All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order
received
Data is transferred to/from the AT88SA102S least significant bit first on the bus
In this document, the most significant bit and/or byte appears towards the left hand side of the page
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