参数资料
型号: AT89C51IC2-SLSIL
厂商: Atmel
文件页数: 110/140页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
标准包装: 27
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
71
AT89C51IC2
4301D–8051–02/08
Serial Port Interface
(SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features
Features of the SPI Module include the following:
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Eight programmable Master clock rates
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Write collision flag protection
Signal Description
Figure 26 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.
Figure 26. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
Slave 1
M
IS
O
M
O
S
I
S
C
K
S
MISO
MOSI
SCK
SS
P
O
R
T
0
1
2
3
Slave 3
M
IS
O
M
O
S
I
S
C
K
S
Slave 4
M
IS
O
M
O
S
I
S
C
K
S
Slave 2
M
IS
O
M
O
S
I
S
C
K
S
VDD
Master
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