参数资料
型号: AT89C51RC-24AU
厂商: Atmel
文件页数: 3/36页
文件大小: 0K
描述: MCU 8051 32K FLASH 5.5V 44-VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 160
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 24MHz
连通性: SPI,UART/USART
外围设备: WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
配用: AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
11
1920D–MICRO–6/08
AT89C51RC
With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combina-
tion with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not
affect ports P0, P2, P3.6 (WR), and P3.7 (RD). For example, with EXTRAM = 0,
MOVX@R0, # data
where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory.
An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will be per-
formed with the MOVX DPTR instructions in the same way as in the standard 80C51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals (see Figure
7-1).
Figure 7-1.
Internal and External Data Memory Address (with EXTRAM = 0)
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard 80C51.
MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins
can be used to output higher-order address bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 outputs the high-order 8 address bits (the
contents of DP0H), while Port 0 multiplexes the low-order 8 address bits (the contents of DP0L)
with data. MOVX@Ri and MOVX@DPTR will generate either read or write signals on P3.6 (WR)
and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.
8.
Hardware Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
ERAM
256 BYTES
UPPER
128 BYTES
INTERNAL
RAM
LOWER
128 BYTES
INTERNAL
RAM
FF
00
FF
80
00
SPECIAL
FUNCTION
REGISTER
FF
80
EXTERNAL
DATA
MEMORY
FFFF
0100
0000
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