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| 型号： | AT89EB5114-TGSIL |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Low-pin-count 8-bit microcontroller with A/D converter |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SO-20 |
| 文件页数： | 24/95页 |
| 文件大小： | 1126K |
| 代理商： | AT89EB5114-TGSIL |
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24
4311A–8051–01/05
Timers/Counters
Introduction
The AT8xEB5114 implements two general-purpose, 16-bit Timers/Counters. Although
they are identified as Timer 0, Timer 1, they can be independently configured each to
operate in a variety of modes as a Timer or as an event Counter. When operating as a
Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt
request. When operating as a Counter, a Timer/Counter counts negative transitions on
an external pin. After a preset number of counts, the Counter issues an interrupt
request.
The Timer registers and associated control registers are implemented as addressable
Special Function Registers (SFRs). Two of the SFRs provide programmable control of
the Timers as follows:
Timer/Counter mode control register (TMOD) and Timer/Counter control register
(TCON) control both Timer 0 and Timer 1.
The various operating modes of each Timer/Counter are described below.
Timer/Counter
Operations
A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to
form a 16-bit Timer. Setting the run control bit (TRx) in the TCON register (see
Figure 15) turns the Timer on by allowing the selected input to increment TLx. When
TLx overflows it increments THx and when THx overflows it sets the Timer overflow flag
(TFx) in the TCON register. Setting the TRx does not clear the THx and TLx Timer reg-
isters. Timer registers can be accessed to obtain the current count or to enter preset
values. They can be read at any time but the TRx bit must be cleared to preset their val-
ues, otherwise the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down system clock or the external pin Tx as the source for the counted signal.
The TRx bit must be cleared when changing the operating mode, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down system
clock. The Timer register is incremented once every peripheral cycle.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on
the external input pin Tx. The external input is sampled during every S5P2 state. The
Programmer’s Guide describes the notation for the states in a peripheral cycle. When
the sample is high in one cycle and low in the next one, the Counter is incremented. The
new count value appears in the register during the next S3P1 state after the transition
has been detected. Since it takes 12 states (24 oscillator periods in X1 mode) to recog-
nize a negative transition, the maximum count rate is 1/24 of the oscillator frequency in
X1 mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
Timer 0
Timer 0 functions as either a Timer or an event Counter in four operating modes.
Figure 7 to Figure 10 show the logic configuration of each mode.
Timer 0 is controlled by the four lower bits of the TMOD register (see Figure 16) and bits
0, 1, 4 and 5 of the TCON register (see Figure 15). The TMOD register selects the
method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and the operating
mode (M10 and M00). The TCON register provides Timer 0 control functions: overflow
flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer
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