参数资料
型号: AT89LS8252-12JI
厂商: Atmel
文件页数: 6/35页
文件大小: 0K
描述: IC 8051 MCU FLASH 8K 44PLCC
标准包装: 27
系列: 89LS
核心处理器: 8051
芯体尺寸: 8-位
速度: 12MHz
连通性: SPI,UART/USART
外围设备: POR,WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
其它名称: AT89LS825212JI
AT89LS8252
0850C–MICRO–3/06
14
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu-
lar I/0 pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 3
MHz at a 12 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 rollovers will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
UART
The UART in the AT89LS8252 operates the same way as
the UART in the AT89C51, AT89C52 and AT89C55. For
further information, see the October 1995 Atmel Microcon-
troller Data Book, page 2-49, section titled, “Serial Inter-
face.”
Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the AT89LS8252 and
peripheral devices or between several AT89LS8252
devices. The AT89LS8252 SPI features include the follow-
ing:
Full-Duplex, 3-Wire Synchronous Data Transfer
Master or Slave Operation
1.5-MHz Bit Frequency (max.)
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wakeup from Idle Mode (Slave Mode Only)
Clock-Out Frequency
Oscillator Frequency
4
65536
RCAP2H,RCAP2L
()
[]
×
-------------------------------------------------------------------------------------------
=
Figure 6. SPI Block Diagram
OSCILLATOR
8/16-BIT SHIFT REGISTER
READ DATA BUFFER
PIN
CONTR
OL
LOGIC
SPI CONTROL
SPI STATUS REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
SELECT
SPI CLOCK (MASTER)
DIVIDER
÷4÷16÷64÷128
SPI CONTROL REGISTER
8
SPIF
WCOL
SPR1
MSTR
SPIE
CLOCK
LOGIC
CLOCK
MSB
S
M
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
MSTR
SPE
DORD
LSB
S
M
S
MISO
P1.6
MOSI
P1.5
SCK
1.7
SS
P1.4
SPR0
SPE
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