参数资料
| 型号： | AT89S8253-24AC |
| 厂商： | Atmel |
| 文件页数： | 15/60页 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU FLASH 12K 44TQFP |
| 标准包装： | 160 |
| 系列： | 89S |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 24MHz |
| 连通性： | SPI，UART/USART |
| 外围设备： | POR，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 12KB（12K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 44-TQFP |
| 包装： | 托盘 |
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22
3286P–MICRO–3/10
AT89S8253
Table 13-1.
PCON – Power Control Register
PCON Address = 87H
Reset Value = 00xx 0000B
Bit Addressable
SMOD1
SMOD0
–
POF
GF1
GF0
PD
IDL
Bit
7
65
43
21
0
Symbol
Function
SMOD1
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
POF
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST (i.e. warm reset).
GF1, GF0
General-purpose Flags
PD
Power-down bit. Setting this bit activates power-down operation.
IDL
Idle Mode bit. Setting this bit activates Idle mode operation
Table 13-2.
SCON – Serial Port Control Register
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
T1
RI
Bit
7
65
43
21
0
(SMOD0 = 0/1)(1)
Symbol
Function
FE
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD0.
SM0
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM2
Enables the Automatic Address Recognition feature in modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode
0, RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
Mode
Description
Baud Rate(2)
0
shift register
fosc/12
0
1
8-bit UART
variable
1
0
2
9-bit UART
fosc/64 or fosc/32
1
3
9-bit UART
variable
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| AT89S8253-24AU | 功能描述:8位微控制器 -MCU 12kB Flash 256B RAM 2.7V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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