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| 型号： | AT91RM9200-CJ-002 |
| 厂商： | Atmel |
| 文件页数： | 15/41页 |
| 文件大小： | 0K |
| 描述： | IC ARM MCU 16BIT 128K 256BGA |
| 产品培训模块： | SAM9 MPU Boot Solutions & Application Deployment MCU Product Line Introduction |
| 标准包装： | 126 |
| 系列： | AT91 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 180MHz |
| 连通性： | EBI/EMI，以太网，I²C，MMC，SPI，SSC，UART/USART，USB |
| 外围设备： | POR |
| 输入/输出数： | 122 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | ROM |
| RAM 容量： | 48K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 256-BGA |
| 包装： | 托盘 |
| 配用： | AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9 |
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22
1768MS–ATARM–09-Jul-09
AT91RM9200
10.3
Peripheral Multiplexing on PIO Lines
The AT91RM9200 features four PIO controllers:
PIOA and PIOB, multiplexing I/O lines of the peripheral set
PIOC, multiplexing the data bus bits 16 to 31 and several External Bus Interface control
signals. Using PIOC pins increases the number of general-purpose I/O lines available but
prevents 32-bit memory access
PIOD, available in the 256-ball BGA package option only, multiplexing outputs of the
peripheral set and the ETM port
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The tables in the following paragraphs define how the I/O lines of the peripher-
als A and B are multiplexed on the PIO Controllers A, B, C and D. The two columns “Function”
and “Comments” have been inserted for the user’s own comments; they may be used to track
how pins are defined in an application.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If equal to “I/O”, the PIO line resets in input with the pull-up enabled so that the device is
maintained in a static state as soon as the NRST pin is asserted. As a result, the bit correspond-
ing to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is in the “Reset State” column, the PIO line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, either
address lines or chip selects, and that require the pin to be driven as soon as NRST raises. Note
that the pull-up resistor is also enabled in this case.
24
EMAC
Ethernet MAC
25
AIC
Advanced Interrupt Controller
IRQ0
26
AIC
Advanced Interrupt Controller
IRQ1
27
AIC
Advanced Interrupt Controller
IRQ2
28
AIC
Advanced Interrupt Controller
IRQ3
29
AIC
Advanced Interrupt Controller
IRQ4
30
AIC
Advanced Interrupt Controller
IRQ5
31
AIC
Advanced Interrupt Controller
IRQ6
Table 10-1.
Peripheral Identifiers (Continued)
Peripheral
ID
Peripheral
Mnemonic
Peripheral
Name
External
Interrupt
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT91RM9200CJ100 | 制造商:Atmel Corporation 功能描述: |
| AT91RM9200CJ101 | 制造商:Atmel Corporation 功能描述: |
| AT91RM9200-CJ-101 | 制造商:Atmel 功能描述:MCU 32-bit 91R ARM920T RISC 128KB ROM 1.8V/3.3V 256-Pin BGA |
| AT91RM9200CU002 | 制造商:Atmel Corporation 功能描述: |
| AT91RM9200-CU-002 | 制造商:Atmel Corporation 功能描述:BGA IND TEMP - Trays |
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