参数资料
型号: AT91RM9200-CJ-002
厂商: Atmel
文件页数: 20/41页
文件大小: 0K
描述: IC ARM MCU 16BIT 128K 256BGA
产品培训模块: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
标准包装: 126
系列: AT91
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 180MHz
连通性: EBI/EMI,以太网,I²C,MMC,SPI,SSC,UART/USART,USB
外围设备: POR
输入/输出数: 122
程序存储器容量: 128KB(128K x 8)
程序存储器类型: ROM
RAM 容量: 48K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 256-BGA
包装: 托盘
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
27
1768MS–ATARM–09-Jul-09
AT91RM9200
10.3.5
System Interrupt
The System Interrupt is the wired-OR of the interrupt signals coming from:
the Memory Controller
the Debug Unit
the System Timer
the Real-Time Clock
the Power Management Controller
The clock of these peripherals cannot be controlled and the Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.3.6
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ6, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.4
External Bus Interface
Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– Burst Flash Controller
Additional logic for NAND Flash/SmartMedia and CompactFlash support
Optimized External Bus:
– 16- or 32-bit Data Bus
– Up to 26-bit Address Bus, up to 64-Mbytes addressable
– Up to 8 Chip Selects, each reserved to one of the eight Memory Areas
– Optimized pin multiplexing to reduce latencies on External Memories
Configurable Chip Select Assignment:
– Burst Flash Controller or Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support
– Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support
– Static Memory Controller on NCS7
10.5
Static Memory Controller
External memory mapping, 512-Mbyte address space
Up to 8 Chip Select Lines
8- or 16-bit Data Bus
Remap of Boot Memory
Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Two different Read Protocols for each Memory Bank
Multiple device adaptability
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