参数资料
型号: AT91RM9200-EK
厂商: Atmel
文件页数: 6/41页
文件大小: 0K
描述: DEVEL KIT
标准包装: 1
系列: ARM®, Thumb®
类型: MCU
适用于相关产品: ARM920T
所含物品: 开发板,AC 适配器,线缆以及软件
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
其它名称: Q2427672
14
1768MS–ATARM–09-Jul-09
AT91RM9200
6.4
PIO Controller A, B, C and D Lines
All the I/O lines PA0 to PA31, PB0 to PB29, PC0 to PC31 and PD0 to PD27 integrate a program-
mable pull-up resistor of 15 kOhm typical. Programming of this pull-up resistor is performed
independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that must be enabled as peripherals at
reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing
tables.
7.
Processor and Architecture
7.1
ARM920T Processor
ARM9TDMI
-based on ARM Architecture v4T
Two instruction sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
16-Kbyte Data Cache, 16-Kbyte Instruction Cache
– Virtually-addressed 64-way Associative Cache
– 8 words per line
– Write-though and write-back operation
– Pseudo-random or Round-robin replacement
– Low-power CAM RAM implementation
Write Buffer
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
Standard ARMv4 Memory Management Unit (MMU)
– Access permission for sections
– Access permission for large pages and small pages can be specified separately for
each quarter of the pages
– 16 embedded domains
– 64 Entry Instruction TLB and 64 Entry Data TLB
8-, 16-, 32-bit Data Bus for Instructions and Data
7.2
Debug and Test
Integrated EmbeddedICE
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