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参数资料
| 型号： | ATF1508ASL-20JC84 |
| 厂商： | Atmel |
| 文件页数： | 31/31页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128 MACROCELL LP 84PLCC |
| 标准包装： | 15 |
| 系列： | ATF15xx |
| 可编程类型： | 系统内可编程（最少 10,000 次编程/擦除循环） |
| 最大延迟时间 tpd(1)： | 20.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 宏单元数： | 128 |
| 输入/输出数： | 64 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC（29.31x29.31） |
| 包装： | 管件 |
| 产品目录页面： | 608 (CN2011-ZH PDF) |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
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9
ATF1508AS(L)
0784P–PLD–7/05
ISP
Programming
Protection
The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition the pin-keeper option preserves the
former state during device programming.
All ATF1508AS devices are initially shipped in the erased state thereby making them ready to
use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
JTAG-BST
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The
ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP con-
troller is automatically reset at power-up. The six JTAG BST modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508AS is imple-
mented using the Boundary-scan Definition Language (BSDL) described in the JTAG
specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can
be used to perform BST on the ATF1508AS.
The ATF1508AS also has the option of using four JTAG-standard I/O pins for In-System pro-
gramming (ISP). The ATF1508AS is programmable through the four JTAG pins using
programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG
Boundary-scan
Cell (BSC)
Testing
The ATF1508AS contains up to 96 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update regis-
ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the (BST) capture registers. Input to the cap-
ture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by
the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are
shown below.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF1508ASL-20QC100 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL w/ISP LOW PWR 5V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-20QC160 | 功能描述:CPLD - 复杂可编程逻辑器件 128 MACROCELL w/ISP LO-PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-25AI100 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL 5V 25NS IND TEMP RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-25AI160 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| ATF1508ASL-25AU100 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL w/ISP LOW PWR 5V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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