参数资料
| 型号： | ATF16V8C-7XU |
| 厂商： | Atmel |
| 文件页数： | 20/23页 |
| 文件大小： | 0K |
| 描述： | IC PLD 7NS 20TSSOP |
| 标准包装： | 74 |
| 系列： | 16V8 |
| 可编程类型： | EE PLD |
| 宏单元数： | 8 |
| 输入电压： | 5V |
| 速度： | 7ns |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
6
0425H–PLD–3/11
Atmel ATF16V8C
7.
Power-up reset
Registers of the ATF16V8C are designed to reset during power-up. At a point delayed slightly from V
CC crossing VRST, all
registers will be reset to the low state. As a result, the registered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty
of how V
CC actually rises in the system, the following conditions are required:
1.
The V
CC rise must be monotonic, from below 0.7V
2.
After reset occurs, all input and feedback setup times must be met before driving the clock term high, and
3.
The signals from which the clock is derived must remain stable during t
PR
Figure 8.
Power-up reset
Table 8-1.
Power-up reset parameters
9.
Power-down mode
The ATF16V8C includes an optional pin controlled powerdown feature. Device pin 4 may be configured as the power-
down pin. When this feature is enabled and the power-down pin is high, total current consumption drops to less than
100μA. In the power-down mode, all output data and internal logic states are latched and held. All registered and
combinatorial output data remains valid. Any outputs that were in a high-Z state at the onset of power-down will remain at
high-Z. During power-down, all input signals except the power-down pin are blocked. The input and I/O pin-keeper circuits
remain active to insure that pins do not float to indeterminate levels. This helps to further reduce system power.
Selection of the power-down option is specified in the ATF16V8C logic design file. The logic compiler will include this option
selection in the otherwise standard 16V8 JEDEC fuse file. When the power-down feature is not specified in the design file,
pin 4 is available as a logic input, and there is no power-down pin. This allows the ATF16V8C to be programmed using any
existing standard 16V8 fuse file.
Note:
Some programmers list the JEDEC-compatible 16V8C (No PD used) separately from the non-JEDEC compatible 16V8CEXT.
(EXT for extended features.)
10.
Registered output preload
Registers of the ATF16V8C are provided with circuitry to allow loading of each register with either a high or a low. This
feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with
preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will
be done automatically by approved programmers.
Parameter
Description
Typ
Max
Units
t
PR
Power-up
Reset Time
600
1,000
ns
V
RST
Power-up
Reset Voltage
3.8
4.5
V
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