参数资料
型号: ATMEGA6490V-8AI
厂商: Atmel
文件页数: 47/146页
文件大小: 0K
描述: IC AVR MCU FLASH 64K 1.8 100TQFP
产品培训模块: megaAVR Introduction
标准包装: 90
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,LCD,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 托盘
配用: ATSTK600-TQFP100-ND - STK600 SOCKET/ADAPTER 100-TQFP
ATSTK504-ND - STARTER KIT AVR EXP MOD 100P LCD
2010-2012 Microchip Technology Inc.
DS41440C-page 293
PIC16(L)F1825/1829
26.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Programmable clock polarity in synchronous
modes
Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
Automatic detection and calibration of the baud rate
Wake-up on Break reception
13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 26-1 and Figure 26-2.
FIGURE 26-1:
EUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb
LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8)
0
TX9
TRMT
SPEN
TX/CK pin
Pin Buffer
and Control
8
SPBRGL
SPBRGH
BRG16
FOSC
÷ n
n
+ 1
Multiplier
x4
x16 x64
SYNC
1X00 0
BRGH
X110 0
BRG16
X101 0
Baud Rate Generator
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