参数资料
型号: ATTINY13A-SH
厂商: Atmel
文件页数: 47/67页
文件大小: 0K
描述: IC MCU AVR 1K FLASH 20MHZ 8SOIC
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 95
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 6
程序存储器容量: 1KB(512 x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
包装: 管件
产品目录页面: 612 (CN2011-ZH PDF)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
28
8126F–AVR–05/12
ATtiny13A
6.4.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of eight at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the present
operating conditions. Note that any value can be written to the CLKPS bits regardless of the
CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is
chosen if the selcted clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. The device is shipped with the CKDIV8 Fuse
programmed.
Bit
7
6
5
4
3
2
1
0
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
Table 6-8.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
00
0
1
00
0
1
2
00
1
0
4
00
1
8
相关PDF资料
PDF描述
ATTINY13A-SSH IC MCU AVR 1K FLASH 20MHZ 8SOIC
ATTINY13A-SSU IC MCU AVR 1K FLASH 20MHZ 8SOIC
BPBS8B96CAP1LF BPBS8B96CAP1LF COVER KIT 96P LF
HM2SC25A8LF HM2SC25A8LF MILLIPACS SHIELDING
HM2SC22A8LF MILLIPACS 2R SHIELDING
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