参数资料
型号: ATTINY13A-SSH
厂商: Atmel
文件页数: 67/67页
文件大小: 0K
描述: IC MCU AVR 1K FLASH 20MHZ 8SOIC
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 100
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 6
程序存储器容量: 1KB(512 x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 612 (CN2011-ZH PDF)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
9
8126F–AVR–05/12
ATtiny13A
4.3.1
SREG – Status Register
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
Bit
7
65
43
21
0
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
R/WR/W
Initial Value
0
相关PDF资料
PDF描述
ATTINY13A-SSU IC MCU AVR 1K FLASH 20MHZ 8SOIC
BPBS8B96CAP1LF BPBS8B96CAP1LF COVER KIT 96P LF
HM2SC25A8LF HM2SC25A8LF MILLIPACS SHIELDING
HM2SC22A8LF MILLIPACS 2R SHIELDING
HM2SC25B HM2SC25B-HM2 SHIELDING COVER
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