参数资料
| 型号： | ATTINY15L-1PC |
| 厂商： | Atmel |
| 文件页数： | 57/85页 |
| 文件大小： | 0K |
| 描述： | IC AVR MCU 1K FLASH 2.7V 8DIP |
| 标准包装： | 50 |
| 系列： | AVR® ATtiny |
| 核心处理器： | AVR |
| 芯体尺寸： | 8-位 |
| 速度： | 1.6MHz |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 6 |
| 程序存储器容量： | 1KB（512 x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 64 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 4x10b |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
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60
ATtiny15L
1187H–AVR–09/07
The device is clocked from the internal clock at the uncalibrated minimum frequency
(0.8 - 1.6 MHz). The minimum low and high periods for the serial clock (SCK) input are
defined as follows:
Low: > 2 MCU clock cycles
High: > 2 MCU clock cycles
Low-voltage Serial
Programming Algorithm
When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK.
When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See
Figure 34, Figure 35, and Table 28 for timing details. To program and verify the
ATtiny15L in the Serial Programming mode, the following sequence is recommended
(See 4-byte instruction formats in Table 27):
1.
Power-up sequence:
Apply power between V
CC and GND while RESET and SCK are set to “0”. If the pro-
grammer cannot guarantee that SCK is held low during Power-up, RESET must be
given a positive pulse of at least two MCU cycles duration after SCK has been set to
“0”.
2.
Wait for at least 20 ms and enable serial programming by sending the Program-
ming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section
for minimum low and high periods for the serial clock input SCK.
3.
The serial programming instructions will not work if the communication is out of
synchronization. When in sync, the second byte ($53) will echo back when issu-
ing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
4.
If a Chip Erase is performed (must be done to erase the Flash), wait t
WD_ERASE
after the instruction, give RESET a positive pulse, and start over from step 2.
See Table 29 on page 63 for t
WD_ERASE value.
5.
The Flash or EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate write instruction. An EEPROM
memory location is first automatically erased before new data is written. Use
data polling to detect when the next byte in the Flash or EEPROM can be written.
If polling is not used, wait t
WD_PROG_FL or tWD_PROG_EE, respectively, before trans-
mitting the next instruction. See Table 30 on page 63 for the t
WD_PROG_FL and
t
WD_PROG_EE values. In an erased device, no $FFs in the data file(s) need to be
programmed.
6.
Any memory location can be verified by using the Read instruction, which
returns the content at the selected address at the serial output MISO (PB1) pin.
7.
At the end of the programming session, RESET can be set high to commence
normal operation.
8.
Power-off sequence (if needed):
Set RESET to “1”.
Turn V
CC power off.
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