参数资料
型号: ATTINY4313-SU
厂商: Atmel
文件页数: 5/22页
文件大小: 0K
描述: IC MCU AVR 4K FLASH 20SOIC
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 37
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 18
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
2006 Microchip Technology Inc.
DS30221C-page 11
PIC16F872
Bank 2
100h(2)
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000
101h
TMR0
Timer0 Module Register
xxxx xxxx
102h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
103h(2)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
104h(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
105h
Unimplemented
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
107h
Unimplemented
108h
Unimplemented
109h
Unimplemented
10Ah(1,2) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
10Ch
EEDATA
EEPROM Data Register Low Byte
xxxx xxxx
10Dh
EEADR
EEPROM Address Register Low Byte
xxxx xxxx
10Eh
EEDATH
EEPROM Data Register High Byte
xxxx xxxx
10Fh
EEADRH
EEPROM Address Register High Byte
xxxx xxxx
Bank 3
180h(2)
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
183h(2)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
184h(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
185h
Unimplemented
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
Unimplemented
188h
Unimplemented
189h
Unimplemented
18Ah(1,2) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18Ch
EECON1
EEPGD
WRERR
WREN
WR
RD
x--- x000
18Dh
EECON2
EEPROM Control Register2 (not a physical register)
---- ----
18Eh
Reserved; maintain clear
0000 0000
18Fh
Reserved; maintain clear
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These bits are reserved; always maintain these bits clear.
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